Sr. Staff Software R&D Engineer-Extraction

USA – California – Mountain View/Sunnyvale, USA – Oregon – Hillsboro

Job Description and Requirements

At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.

We’re looking for StarRC Extraction R&D Engineer to join the team.
Does this sound like a good role for you?

In this role: You will be a member of a high performing R&D team contributing to the development of market-leading interconnect parasitic extraction tool (StarRC).

StarRC™ is the EDA industry’s gold standard for parasitic extraction. A key component of Synopsys Design Platform, it provides a silicon accurate and high-performance extraction solution for SoC, custom digital, analog/mixed-signal and memory IC designs. StarRC offers modeling of physical effects for advanced process technologies, including FinFET technologies at 16 nm, 14 nm, 10 nm, 7 nm, and beyond. Its seamless integration with industry standard digital and custom implementation systems, timing, signal integrity, power, physical verification and circuit simulation flows delivers unmatched ease-of-use and productivity to speed design closure and signoff verification.

Key Qualifications:   

• Research, design, and development of brand-new extraction capabilities with special focus on   transistor level modeling.
• Designing very efficient data structure and algorithms
• Collaboration with other market leading product developers in layout design, simulations, timing/reliability verification areas
• Communication with variety of customers on resolution of challenging problems in CPU design/validation/signoff/etc.
• MS/PhD with CS/CE/EE with 5+ years of relevant CAD/EDA software development experience.
• Relevant experience and background in transistor level extraction / modeling Proficiency

Preferred Experience:

• Design/Analysis of superconducting electronic circuits
• Transistor modeling from physical structure
• Circuit resistance and capacitance calculation from physical structure
• Semiconductor processing
• Transmission line analysis