Principal Physical Design Engineer

What You’ll Do as a Senior CAD Flow Implementation Engineer for SoCs

Join our innovative engineering team and contribute to the development of highly configurable semiconductor IP used in advanced System-on-Chip (SoC) designs. In this role, you will focus on the generation, implementation, and verification of physical design collateral and flows for cutting-edge semiconductor products.

You will collaborate closely with hardware and software engineering teams to improve physical implementation methodologies, debug complex integration issues, and ensure high-quality deliverables across multiple EDA toolchains.

Job benefits:

• You’ll work on FlexNoC, the market-leading product in system IP.
• You’ll play a critical role supporting a large number of clients such as AMD, Samsung, Altera, Microchip, Toshiba, etc.
• You’ll get hands-on with a wide range of EDA tools: Design Compiler, Genus, etc.
• You’ll enjoy a high level of autonomy and receive training to build your skills in the technologies you’re least familiar with.
• You’ll always have support whenever you have questions. The team currently consists of 7 people.
• You’ll work within an ambitious international group with numerous opportunities for growth.

Key Responsibilities

• Develop, maintain, and debug physical implementation flows and constraints using third-party EDA tools from vendors such as Cadence and Synopsys.
• Define, document, develop, and execute verification tests for physical implementation flows and system-level coverage.
• Analyze implementation quality metrics and validate results across multiple configurations.
• Debug implementation issues, regressions, and tool-flow related problems.
• Contribute to the continuous improvement of methodologies, implementation strategies, and automation flows aligned with modern semiconductor design practices.
• Collaborate with hardware and software engineering teams to resolve hardware/software compatibility and interface issues.
• Interact with internal users and stakeholders to define system requirements, support flow evolution, and provide maintenance guidance.
• Support process documentation and contribute to engineering best practices.

What You Bring

• 5+ years of experience in digital IC design and physical implementation.
• Strong knowledge of physical implementation flows and EDA tools such as Cadence and Synopsys (Proficiency in Design Compiler/Fusion Compiler or Genus is required).
• Expertise in physical design debugging and implementation analysis.
• Strong understanding of timing constraints, STA concepts, and timing analysis methodologies.
• Experience with hardware description and scripting languages including Python, RTL and TCL.
• Strong analytical, debugging, and problem-solving skills.
• Excellent communication and collaboration abilities.
• Ability to work autonomously in a fast-paced engineering environment.

Bonus Points If You Have

• Experience with highly configurable IP or SoC integration flows.
• Familiarity with verification methodologies and coverage-driven validation.
• Experience improving CI/CD or automation flows for semiconductor implementation environments.
• Exposure to advanced process nodes and low-power implementation techniques.

Education Requirements

• Master’s degree or PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field.

Estimated Base Salary

€50,000 to €70,000 annually. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.