- Develop and implement physical design techniques for high performance processor.
- The candidate will learn about ASIC design methodology, flows and implementation using state-of-the art synthesis, place-and-route tools.
- The candidate will also be exposed to the Xtensa proccessor IP and DSP technology.
- The candidate will work closely with a mentor to use the Cadence Tensilica IP’s design automation flow.
- Strong understanding of processor architechture, digital circuit design is required.
- Exposure to EDA implementation and simulation tools is useful.
- Hands on experience with programming languages (C/C++) and scripting languages (Perl, Tcl) is a plus.
- The candidate is required to be hands on and self motivated.
- M.S. in EE/CS or related field (current M.S. students will be considered).
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To view the job application please visit cadence.wd1.myworkdayjobs.com.