Manager Design Hardware – Principal HW Engineer

Arteris enables engineering and design teams at the world’s most transformative brands to connect and integrate today’s system-on-chips (SoCs) that fuel modern innovation.

If you’ve held a smartphone, driven an electronic car, or powered up a smart TV, you’ve come in contact with what we do at Arteris. Here, the future is quite literally in your hands—and when it isn’t, chances are it is flying overhead in a drone, a satellite, or in the cloud at a datacenter!

As a Manager Design Hardware / Principal Hardware Engineer at Arteris your role will be:

The role involves leading the team of hardware engineers in specifying ARTERIS hardware components, defining their architecture and contributing to their software description. The degree of innovation must enable the regular generation of patents. His technical expertise enables him to support customer and supplier discussions, and to keep a technological watch on the entire IP portfolio.

Key Responsibilities:

• Write architecture specifications for highly configurable on-chip networks, respecting the most stringent coverage requirements in design verification.
• Develop or update interconnect protocols to meet next-generation SoC requirements.
• Work closely with modeling and design teams to maintain market leadership in NoC performance, power and area.
• Contribute regularly to the Arteris patent portfolio.
• Support technical discussions with customers and suppliers.
• Monitor market developments and the latest innovations.
• Maintain and improve the library of basic hardware elements that can be reused by the whole team.
• Team management: recruitment, training, coaching and development of employees.
• Specify system IPs and the methods for implementing them.
• Design their architecture.
• Supervise development and verification.
• Validate that PPA criteria are met.
• Draft and register associated patents.
• Monitor technological developments.
• Provide technical support for discussions with customers and suppliers.
• Team management.

Experience Requirements / Qualifications:      

• Over 16 years’ experience in digital circuit design.
• Aptitude for team management.
• Experience in coherent and non-coherent communication protocols and control models (e.g. AMBA, PCIe, CXL, OCP, others) as well as CPU architectures (ARM/RISC V).
• Strong experience in SoC/IP design flow (e.g. specification, architecture, RTL coding, verification, DFT, synthesis, power and timing closure).
• Excellent problem solving, strong communication and teamwork skills.
• Autonomous, able to work with minimum supervision.
• Knowledge of SystemC, Verilog/VHDL/System Verilog, Cadence/Synopsys/Mentor Graphic (backend tools), C++, Python, scripting languages.

Education Requirements:

Master’s degree or Doctorate in engineering or computer science

Other Requirements: