Job Description and Requirements
In this role you will be working on providing technical support to customers for integration of Synopsys’ Mixed Signal IP into ASICs including:
- Debugging of customers’ simulation or silicon issues.
- Reviewing customers’ integration of our IP.
- Logical and Physical integration.
- Answering technical questions about our IPs’ operation and features.
- Training field engineers in IP operation and demonstration.
- Interfacing with R&D and Product Engineering teams to provide timely communication to and from customers.
- BSEE 7+ years of prior work-experience, or MS +5 years of prior work-experience.
- RTL design & verification in Verilog, Synthesis, Static-Timing Analysis, DFT, CDC.
- Scripting in Perl/TCL/Python etc.
- Time management skills to balance multiple high-priority tasks and projects.
- Excellent oral and written communication skills.
- Willingness to learn new skills and perform tasks that often go outside of the area of current expertise.
Domain-knowledge: High-speed serial communication standards like USB2.0, HSIC, USB3.0, USB3.1, Type-C, Alternate mode etc.., with full understanding of functional partitioning between protocol layers.
- DRC, LVS, ERC, PERC, understanding of double patterning.
- Analog design/simulation.
- HSPICE, XA-RA.
- Understanding of transmission-line fundamentals, and signal-integrity concepts.
- Lab experience.
- Familiarity with ATE concepts and test program flow.
Apply for job
To view the job application please visit sjobs.brassring.com.