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Block Level Verification Engineer

Block Level Verification Engineer
by macvin on 05-19-2020 at 4:12 am

Develop block level test plan, UVM test bench components such as agents(drivers/monitors), scoreboard, constrained random testcases based on UVM sequences, assertions.

Develop and close functional coverage, code coverage. Ability to independently execute
on test plan, run simulations and debug.

 7+ years of ASIC verification experience
 UVM/System Verilog
 VCS simulator, Verdi
 2, 3 projects experience with UVM based testbench, coverage closure

 Previous experience with PCIe, Ethernet, HBM-DDR, Processor verification,
floating point computational unit highly desired
 C/C++ experience is desired
 Scripting skills(Perl, Python)
 Formal verification experience is a plus

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To apply for this job email your details to macvin@crabsassociates.com

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