Join our upcoming webinar on JESD204 and get insights into what we predict the upcoming JESD204D standard will contain, based on many years of experience working with JESD204.
Our expert speaker, Piotr Koziuk, has over a decade of experience with JESD204 standards and is a member of the JEDEC Standardization Committee. He will share his prediction of what could be the features of the JESD204D and explain potentially how the new architecture will improve the Bit Error Rate (BER) through Reed Solomon Forward Error Correction (RS-FEC) and new framing and data encoding patterns.
Also briefly touch upon eXtreme Short Reach (XSR) for Die-to-Die or 2.5D Chip-to-Chip stacking applications originating from the underlying 112G OIF Serdes Specifications and cover how the standard will potentially target various reach classes for PAM4 and NRZ encoding and the higher line rates.
Don’t wait to register for this must-attend webinar, happening on April the 11th and 12th.
Register for April 11 th – 11 AM EAST, 8 AM PST – USA
Register for April 12 th – 5 PM China Time, 6 PM Japan & Korea
About Comcores
Comcores is a Key supplier of digital IP Cores and solutions for digital subsystems with a focus on Ethernet Solutions, Wireless Fronthaul and C-RAN, and Chip to Chip Interfaces. Comcores’ mission is to provide best-in-class, state-of-the-art, quality components and solutions to ASIC, FPGA, and System vendors. Thereby drastically reducing their product cost, risk, and time to market. Our long-term background in building communication protocols, ASIC development, wireless networks and digital radio systems has brought a solid foundation for understanding the complex requirements of modern communication tasks. This know-how is used to define and build state-of-the-art, high-quality products used in communication networks.
To learn more about this solution from Comcores, please contact us at sales@comcores.com or visit www.comcores.com
Also Read:
WEBINAR: O-RAN Fronthaul Transport Security using MACsec
WEBINAR: Unlock your Chips’ Full Data Transfer Potential with Interlaken
Bridging Analog and Digital worlds at high speed with the JESD204 serial interface
Share this post via:
Next Generation of Systems Design at Siemens