Analog Bits at the 2024 Design Automation Conference

Analog Bits, the industry’s leading provider of low-power mixed-signal IP solutions will be demonstrating several IP’s in TSMC advanced nodes at DAC. Analog Bits is also a long time DAC supporter and very active in the semiconductor and on SemiWiki, absolutely. Great company!

As power management and energy efficiency is getting critical for AI and ML chips, Analog Bits has developed several novel IP’s in advanced processes to better monitor and manage power. The newest LDO IP, Power supply droop detectors, Embedded Clock LC PLL’s in TSMC N3P process and will be demonstrating working silicon results from test chips at their booth at DAC. Additionally there will be demonstration is showcasing Analog Bits’ industry leading portfolio of Mixed Signal IP in advanced 3nm, 4nm, 5nm, and Automotive processes.

As more designs are going to multicore architectures, managing power for all those cores becomes important. The new LDO macro can be scaled, arrayed, and shared adjacent to CPU cores and to simultaneously monitor power supply health. With Analog Bits’ detector macros, power can be balanced in real time. Mahesh Tirupattur, Executive Vice President at Analog Bits said, “It is like PLL’s that maintain clocking stability we have are now able to offer IP’s to maintain power integrity in real time.”

Features of the new LDO macro include:

Integrated voltage reference for precision stand-alone operation
Easy to integrate, use, and configure with no additional components or special power requirements
Scalable for multiple output currents
Programmable output level
Trimmable
Implemented with Analog Bits’ proprietary architecture
Requires no additional on-chip macros, minimizing power consumption

Analog Bits’ Droop Detector addresses SoC power supply and other voltage droop monitoring needs. The Droop Detector macro includes an internal bandgap style voltage reference circuit which is used as a trimmed reference to compare the sampled input voltage against.

The part is synchronous with latched output. Only when the monitored voltage input has exceeded a user-selected voltage level will the Droop Detector output signal indicate that a violation is detected.

In gate-all-around architectures there will be only one gate oxide thickness available to support the core voltage of the chip. Other oxide thicknesses to support higher voltages are simply no longer available. In this scenario, the Pinless Technology invented by Analog Bits will become even more critical to migrate below 3nm as all of the pinless IP will work directly from the core voltage.

The Pinless PVT Sensor at TSMC N5 and N3 provides full analog process, voltage, and temperature measurements with no external pins access required by running off the standard core power supply. This approach delivers many benefits, including:

No on-chip routing of the analog power supply
No chip bumps
No package traces or pins
No PCB power filters

As the electronic content in automobiles continues to increase, the need for a complete library of IPs that meet the stringent requirements of this operating environment become more important. Analog Bits will showcase a wide range of IP that meets automotive requirements on the TSMC N5A process.

Analog Bits’ Wide Range PLL addresses a large portfolio of applications, ranging from simple clock de-skew and non-integer clock multiplication to programmable clock synthesis for multi-clock generation. This IP is designed for AEC-Q100 Automotive Grade 2 operation.

The PLL macro is implemented in Analog Bits’ proprietary architecture that uses core and IO devices. In order to minimize noise coupling and maximize ease of use, the PLL incorporates a proprietary ESD structure, which is proven in several generations of processes. Eliminating bandgaps and integrating all on-chip components such as capacitors and ESD structure helps the jitter performance significantly and reduces stand-by power.