Last June, the ESD Alliance (ESDA) has released Q1 2016 results for EDA (CAE, PCB & MCM and IC Physical), Silicon IP (SIP) and Services. Not a surprise for Semiwiki readers since 2013, the SIP category is recognized as the largest with $689 million revenues for the quarter, and four-quarters moving average increasing by 11.6 percent. Total ESDA revenues have increased by 4.3%, so I have tried to investigate more deeply the various growth sources. SIP represents $688.7 million out of $1962 million for the four categories, or 35% of the total. Let’s do some simple computing:
The SIP growth contribution is 11.6% * 0.35% = 4,06% of the total growth (94%+).
The total growth is 4.3%, so SIP contribution is 4.06/4.30, or 94.4% of the four quarter moving average increase of total ESDA revenues! If you prefer, EDA four-quarters moving average without SIP would have increased only by 0.24%. Not only SIP is the largest ESDA category, but SIP is responsible for most of ESDA growth, fueling this growth at 94%.
Can we say that the future of EDA is IP? Certainly yes! But let’s see the various consequences derived from this simple fact on Big 3 strategy, Design Automation Conference content or EDA analyst pertinence…
The two most important trends in the semi industry are consolidation (illustrated by recent M&A) and huge investment increase linked with SoC design for the players who have to follow Moore’s law, or at least design on the latest technology nodes, 16FF nm or below. As of today, the transistor cost doesn’t anymore decline when moving down (28nm à 16FF, or 16FF to 10FF), the overall NRE cost are exploding, but the race for integration is still rewarding. Samsung, Apple or Intel have to offer SoC integrating more functions, more CPU cores to stay leaders on the market and provide more power efficient IC (not only faster and delivering more powerful computing, but also offering lower power per MIPS). But the same R&D investment allows developing much less SoC than before (less design starts).
When two semi companies merge, the product port-folio will be optimized and redundancy will be eliminated, leading to less design starts as well. If you are a pure EDA vendor (not selling IP) you will sell fewer tools. In fact, the design tools supporting SoC targeting advanced nodes are more complexes and by consequence more expansive. But if you look at the above curves for “IC Physical” and “CAE” categories, the revenue growth between 2007 (before 2008 crisis) and 2016 has been very modest (less than 10% for the whole period). In other words, selling EDA tools doesn’t bring you enough growth. That’s why two of the big 3, namely Cadence and Synopsys, have strongly developed their respective IP port-folio and are still investing, by IP vendor acquisition and by staffing more and more their IP groups.
I am sure that you have a good question to ask: if we consider semi consolidation and increasing SoC development cost for advanced nodes, both leading to fewer design starts, why should SIP category grow as it did, moving from $280 million by quarter in 2007 to almost $700 in 2015? It’s a paradox!
By analyzing this IP market since 2007, I know that the answer is complex and I will try to explicit it here. The first reason is IP externalization trend. Since the mid 2000’s the chip makers tend to focus on their core competencies and outsource the too complexes functions, like SRAM, eFlash, CPU, GPU, DSP, SerDes, etc, as well as the peripheral functions (like interfaces: USB, PCIe, HDMI, SATA…). The externalization “factor” is growing year after year, but it grows only by 2% to 4% per year (result from IPnest analysis of the IP market since 2007).
There should be other reasons to explain a sustained 10% to 12% yearlygrowth since 2005!
SoC integration has also an important impact. When chip makers move from 40nm to 28nm, 28nm to 16FF and so on, they can develop chip integrating 50% more transistor at every step. It has been shown that EDA tools improvement was not going fast enough to support this higher integration capability, and that you can’t extend the size of a design team indefinitely. IP Reuse was part of the solution, and integrating more and more IP when developing on smaller technology node is a matter of fact, this trend was proven by analyst. In fact, when moving down by one technology node, the number of IP per SoC is growing more than the design start count decrease, the net result (number of IP x Design start count) is higher. This is clearly another growth factor for the IP market.
The last reason explaining IP market growth despite consolidation and development cost increase is quite subtle, but is proven when reviewing the IP market by segment, especially the standard based IP like USB, DDRn, PCIe and more. These IP products, controller and PHY, can escape commoditization thanks to the constant release of new protocol (PCIe 4.0 after PCIe 3.0 for example). At every new protocol release, the product is more complex (the specification is more complicated) and faster. PHY IP running at 16 Gbps is selling at much higher price than this running at 8 Gbps! By reviewing this protocol based IP market since almost 10 years, I can affirm that a PCIe or USB IP product (PHY or controller) license cost has grown constantly. If a PCIe 1.0 Controller IP was selling for $100K in 2006, the PCIe 3.0 version is selling for at least 50% more, if not 100%.
I realize that I have not mentioned another factor, very important for IP vendors offering royalty based business model, like ARM or CEVA. Because the chip cost tend to decrease year after year (for the same function), we don’t realize how strong the pervasion of semiconductor product is in every electronic segment. That simply means that 100’s of million if not billions of new IC integrating CPU, DSP, GPU IP are shipped every year. More products shipped on year N+1 simply mean higher royalties based revenues than on year N, these revenues being accounted in the IP category.
Let’s come to the important point. If the IP category is not only the most important of the EDA market, but also offering most of the growth (94%!), why the DAC committee seem to neglect this important EDA segment? Just take a look at DAC 2016 agenda and you will realize that the percentage of presentation focusing on IP is much lower than the IP market weight in $. The good news is that Michael McNamara, VP of Adapt IP, will be DAC 2017 chairman, so we can expect the next DAC agenda to be more “IP friendly”…
I just want to pass a message to analyst dealing with the EDA market. If the fact that most of the EDA market growth is coming from the IP category is confirmed (and I think it will be), it may be the right time to take a closer look at the IP market… ESL may be a very interesting concept, but this concept will not generate growth the same way IP market will!
Eric Esteve from IPNEST –
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