Agile Analog Visit at #60DAC

Chris Morrison, Director of Product Marketing at Agile Analog met with me on the Tuesday at DAC this year, and I asked what has changed in the last year for their analog IP business. The short answer is that the company has initially built up foundation IP for Analog Mixed-Signal (AMS) uses, then recently added new IP for data conversion, power management and chip monitoring and health.

I was surprised to learn just how much AMS IP they have to offer:

Data Conversion

• 8/10 -bit DAC
• 8/10 bit SAR ADC
• 12 bit SAR ADC

Security

• Voltage glitch detector

Power Management

• Linear Regulator
• Power-On-Reset
• General purpose bandgap
• Power Management (PMU) subsystem
• Sleep Management (SMU) subsystem

Sensing

• Temperature sensor
• Programmable threshold comparator
• PVT sensor subsystem
• IR drop detector
• Sensor interface subsystem

Always-on Domains

• Digital standard cell library
• RC oscillator

There are four initial subsystems and they may be combined to build even bigger systems along with RISC-V support. The interface protocols for Arm’s AMBA APB and SiFive’s TileLink are also supported, so that covers two of the most popular ISA choices out there today.

Chris also talked about some of the current IC design issues like mechanical stress, aging and reliability. What sets Agile Analog apart is the use of their Composa methodology, a rapid way to create new IP blocks based upon customer requirements, Agile Analog’s design recipe and the foundry PDK. So, this automates the front-end of the analog design process quite well, and in the works are further automation for the back-end as well, so stay tuned. New, sized schematics are created for IP blocks in under 10 minutes, which is quite a bit faster than the traditional, manual methods which require weeks of engineering effort. Foundry support for these analog IP blocks are from: TSMC, GlobalFoundries, Intel, Samsung, SMIC, and UMC. .

The Composa tool knows how to combine all of the analog transistors and circuits, just like an expert analog designer would. Connecting your Agile Analog IP blocks is made even easier by wrapping digital logic around the AMS portions, making verification a simpler task. About 50 IP blocks have been delivered to customers, so they are scaling up quickly and efficiently to meet demand.

Last year the company headcount was about 30-35 people, and now it’s grown to over 55, so that says something about their success as a company to meet a challenging market. With a HQ in Cambridge in the UK, the company also has sales offices to help with your questions in Asia, and the US.

In March Agile Analog joined the Intel Found Services (IFS) Accelerator IP Alliance Program, they’re part of the Samsung SAFE and they have just joined the TSMC OIP program too. In 2024 you can expect to see the company continue their growth path across the globe, and even more AMS IP blocks being added to the portfolio, ready to be customized to meet your unique requirements.

Summary

Analog IP has traditionally been a limiting factor in getting new SoCs to market on time and within spec, however with the more automated approach used at Agile Analog you can expect to use their AMS IP at your favorite foundry to speed time to market. Both RISC-V and ARM-based designs can quickly add AMS IP by using subsystems that have been digitally wrapped.

New IP blocks in development include: 12-bit DAC, clock monitor, ultra-low power LDO, ultra-low power bandgap, capless LDO, process sensor and free-running clock. I look forward to talking with Agile Analog again  to give you another update.

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