Synopsys Accelerates First-Pass Silicon Success for Banias Labs’ Networking SoC

Banias Labs is a semiconductor company that develops infrastructure solutions for next-generation communications. Its target market is the high-performance computing infrastructure market including hyperscale data center, networking, AI, optical module, and Ethernet switch SoCs for emerging high-performance computing designs. These SoCs require high-speed Ethernet designs and low-latency solutions to provide increased system performance and accelerate time-to-market. The company has developed an optical DSP SoC on 5nm process technology to address the requirements of this market.

An optical DSP SoC is a specialized type of system-on-chip (SoC) designed for use in high-speed optical communication systems. In addition to the DSP, the optical DSP SoC typically includes high-speed interface IP blocks, such as Ethernet PHY IP, PCIe IP, and DDR memory controllers. These types of SoCs enable high-speed data transfers at low latencies for real-time signal processing. They are also designed to minimize power consumption, making them ideal for applications that require efficient operation with reduced thermal issues. With the advantages come challenges too. The specialized requirements of optical communication systems make designing an optical DSP SoC more challenging than designing a regular SoC.

Implementation Challenges

The challenges revolve around the complexity of the design, the tight power and performance requirements, and the need to meet various industry standards. The integration of multiple IP blocks including the DSP processor, Ethernet PHY IP, and other custom blocks requires careful design and validation. Additional high-speed interfaces such as PCIe and DDR add further to the complexity of the design. The high-speed interfaces and multiple IP blocks in the system can create signal distortion, crosstalk, and electromagnetic interference, which can impact system performance and reliability. Signal and power integrity analysis and optimization must be performed early in the design cycle to ensure that the system can meet its performance and reliability requirements. Finally, meeting time-to-market requirements can be challenging. The high-performance computing infrastructure market is rapidly evolving, and SoC development teams need to deliver their designs quickly to stay ahead of the competition.

Getting to First Pass Silicon Success

Overcoming the above mentioned challenges requires a comprehensive approach. One of the critical components of high-performance, low-latency solutions is the Ethernet PHY IP. The Ethernet PHY IP is responsible for the physical layer interface between the SoC and the Ethernet network. The IP must support high-speed Ethernet interfaces, including 10G, 25G, 40G, 50G, 100G, 200G, 400G, and 800G, and provide low latency and low power consumption. Additionally, the IP must support various standards, including IEEE 802.3 and Ethernet Alliance. Another important component is the EDA design suite. The EDA design suite must provide a comprehensive solution for designing and verifying the SoC, including power optimization, performance analysis, area optimization, and yield analysis. To the extent, the EDA design suite includes advanced features, such as artificial intelligence (AI) and machine learning (ML), the better for enhanced productivity and reduced time-to-market.

Synopsys Accelerates First Pass Silicon Success

Synopsys offers solutions that address the unique challenges of developing SoCs for the high-performance computing infrastructure market. The company provides a comprehensive IP solution that includes a routing feasibility study, packaging substrate guidelines, signal and power integrity models, and thorough crosstalk analysis. This is imperative to address the signal and power integrity challenges faced when developing an optical DSP SoC. Synopsys’ 112G Ethernet PHY IP offers low latency, flexible reach lengths, and maturity on 5nm process technology, making it an ideal solution for hyperscale data center, networking, AI, optical module, and Ethernet switch SoCs. In addition, Synopsys offers an EDA Design Suite that delivers high-quality results with optimized power, performance, area, and yield. Synopsys’ AI-driven EDA Design Suite provides solutions to boost system performance and accelerate time-to-market, making it an essential component of a successful solution for the high-performance computing infrastructure market.

Summary

Synopsys provides high-performance, low-latency solutions that accelerate the development of advanced Ethernet switch and networking SoCs. To learn more about Synopsys’ comprehensive IP solutions, their comprehensive EDA Design Suite and their AI-Enhanced EDA Suite, visit the following pages.

Synopsys’ comprehensive IP solutions

Synopsys’ comprehensive EDA Suite

Synopsys’ AI-driven EDA Design Suite

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