It’s Energy vs. Power that Matters

In tiny devices, such as true wireless headphones, the battery life of the device is usually determined by the chips that execute the device’s functions. Professor Jan Rabaey of UC Berkeley, who wrote the book on low power, also coined the term “energy frugal” a number of years ago, and this term is even more valid today with the proliferation of true wireless devices.

When optimizing the battery lifetime, many times power and energy are used interchangeably. However, they are not interchangeable as the device’s battery stores energy while reducing power can actually consume more energy. Techniques to reduce energy by reducing voltage are being deployed more broadly as demand takes off for true wireless products. In this blog, I’m going to illustrate what’s behind this trend through several examples that demonstrate the relationship between energy, power and voltage.

Let’s start by reviewing the basic equations for energy and power, shown below in Figure 1.  They look similar but there are a few, critical takeaways: 1) energy consumption cannot be reduced by reducing frequency, 2) leakage cannot be reduced without reducing V_DD (excluding process options) and finally, 3) because of the quadratic relationship, V_DD is by far the most effective method of reducing energy.

Figure 1: Basic equations for energy and power

Let’s look at the takeaways with some examples. For takeaway 1), an example is simple: reducing frequency by 10%, for example, increases E_leak by 10% (as t increases 10%) while E_dyn remains unchanged. This “fallacy” is mostly seen in “run-to-complete” strategies. For example, let’s say that your processor consumes 90% dynamic energy and 10% leakage energy at its nominal voltage. If you run to complete (i.e. run the processor as fast as you can) and then let it leak (i.e. no power gating), neither dynamic energy or leakage change (see equation). But the fallacy shows up if you try to run faster for the sake of shutting down earlier.  For example, let’s say a 10% frequency increase for a 10% V_DD increase to run to complete 10% faster. Your new energy consumption is E = 0.9*(1,1)² + 0.1*1.1*0.9 = 119%. Clock gating doesn’t change this equation as it equally affects all dynamic energy cases but let’s look at power gating’s effect. If your power gating switches super-fast and doesn’t cost active energy, then the theoretical maximum you can save is the leakage energy (10%). How about running as fast as you can and then power gating? The dynamic energy increase is quadratic and the leakage linear, so you can’t win. For the 10% frequency increase case above, you would still end up consuming more energy (0.9*(1,1)² + 0 = 109%).

For takeaways 2) and 3) above, let’s turn to examples that employ reduced voltage. These are not hypothetical examples as we are working with companies to deploy solutions based on reduced voltage today.  I’ll need to explain a few assumptions to start.  Assume that your computation time linearly depends on V_DD (a realistic assumption up to a point). Let’s say that this is a slow operating mode (you also have modes that take more of the clock cycle), so your processor (at the same 90% dynamic/ 10% leakage energy as above) finishes in 50% of the clock cycle. Let’s use the remaining 50% of the clock cycle to reduce V_DD (i.e. halve V_DD). This would result in a huge reduction in energy.  For those interested in the exercise: E = 0.9*(0.5)² + 0.1 * 0.5 * 2 = 32.5%. It gets even better,

as I_leak reduces exponentially with voltage. Let’s say that I_leak reduces by 90% when VDD is halved as above. Your new energy is reduced further to only 23.5%. (E = 0.9*(0.5)² + 0.1 * 0.1 (0.5 * 2) = 23.5%)

In case you are thinking that I’m writing this from an ivory tower, there are also cases where reducing voltage does not make sense when looking at the total chip. Let’s say that you have an old PLL which consumes as much energy as your processor but which can be shut off with no leakage. Then the 50% V_DD drop case from above would end up consuming more energy (2*0.5 + 0.5*(0.9*(0.5)² + 0.1 * 0.1 (0.5 * 2)) = 112%). It’s not an uncommon story in the IC industry that the overhead ends up cancelling out the gains, and in upcoming blogs I’ll show you how to avoid that with dynamic voltage and frequency scaling (DVFS) systems based on our experience working with design teams working on true wireless devices.

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