Xilinx has the Power Advantage over Altera

I thought I write about one of the most important subjects in FPGAs, that is power. Power of course is not just based on node size, and it is funny why so many people are concerned about node size. If not just as important is the architectural decisions that drive down power. Do you really care if your part is 16nm or 14nm? Or do you care more about power, performance etc…

Core voltages continue to drop, and serial data rates are going up… way up. Standards, so called, like JESD204b and Hybrid Memory Cube solve many board routing nightmares and power issues BUT chew up an awful lot of GT lanes. I’m not complaining, I hate DDR but this migration highlights the leadership of Xilinx’s Gigabit Transceivers. Xilinx just finished publishing a white paper on the power advantages at their 20nm/16nm node. “Power Reduction in Next-Generation UltraScale Architecture”.

These power reductions are being realized today on real hardware by real customers. They configure and even work. Xilinx’s power performance is not only at 20nm, but below are some nice 28nm charts of how Xilinx does against the ‘competitor’. I wonder who that is?

Back to the serial interfaces that I was all wound up about. The above shows a 4 channel design, At 28 gb/s, Xilinx is running about 800mw and Altera at 1000mw. Yes this is the same node compare, 28nm. Ok, so you say big deal lukey dukey, I don’t care about 200mw. Ok, how about your design that uses 64 lanes for Hybrid Memory cube and another 32 for JESD204b? Power differences just for transceivers begins to add up. We approximately would have 19.2 Watts for Xilinx, and Altera 24 watts. So Xilinx here is 5 watts better. All the green folk just cheered.

Most designers start early in the design cycle having the goal of about being complete when the silicon rolls of the line. That means the quality of tools, specifically the models that yield the power need to be accurate. Interested in seeing how well Xilinx does in model to hardware correlation with respect to power? That is how accurate are the power estimator tools?

Xilinx is rock solid once again. Using the ‘competitors’ tools may leave you with a design that no worky because you no cooley. This is huge and it points to execution once again. The difference is Xilinx set’s design goals and achieves them. The competitor, waits for hardware to come back and then begins to write the data sheet. Like I said earlier, node is not that important. Power, performance and of course tools all lead to a quality of result that only Xilinx can deliver and can be relied upon.

OK, let’s put this all together at the system level shall we?

What more can I say? I always do wonder this, why in the world are you using Altera? I wrote about 28nm power for the most part, and the power separation will only continue coupled with accurate powering modeling from Xilinx. Makes me wonder what type of design you are going to have at 20nm?

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