"Results may vary."
They talk about enabling direct print, but at the same time the 40-step multipatterning (3 masks) was broadcast widely as well.
Intel Foundry Gathers Customers and Partners, Outlines Priorities (Intel Connect Live)
- Thread starter Daniel Nenni
- Start date
They talk about enabling direct print, but at the same time the 40-step multipatterning (3 masks) was broadcast widely as well.
Just talking 18A: Microsoft said last year they were signed on to use it. As did Amazon, and according to their website apparently 7 other people signed on (if you also count the USG stuff). Supposedly double-digit adv packaging design wins. Mediatek on i16 for digital TV and WIFI, and a datacenter/edge customer for i3. Apparently Intel is courting the DRAM guys into doing i3 base dies, courting some more i16 customers, and courting a customer who would be interested in co-developing an easier to use i3. Mediatek said today their experience was positive enough to warrant looking into other technologies. BCOM last summer said they were evaluating 18A, and NVIDIA has on multiple occasions in the past expressed interest and said they liked the test chips they had seen (with no process node specified).
What's so funny about that? The exact result is HIGHLY dependent on your process integration choices. To pick two outliers to demonstrate my point. If you choose to have FS only MMP be 40nm, then your FS+BSP vs full BSPDN cost gap will presumably be a lot smaller since the BSPDN "only" process would still be using DUV double patterning for MMP no matter the process. But if you are at 32nm direct print vs 23nm SALELE, yeah that is a night and day difference in cost."Results may vary."
They talk about enabling direct print, but at the same time the 40-step multipatterning (3 masks) was broadcast widely as well.
Unless you mean just the way it was said? Because I will give you the way it is posted on there is pretty funny.
Just viewing it as a kind of disclaimer, looked like fine print to me.What's so funny about that? The exact result is HIGHLY dependent on your process integration choices. To pick two outliers to demonstrate my point. If you choose to have FS only MMP be 40nm, then your FS+BSP vs full BSPDN cost gap will presumably be a lot smaller since the BSPDN "only" process would still be using DUV double patterning for MMP no matter the process. But if you are at 32nm direct print vs 23nm SALELE, yeah that is a night and day difference in cost.
Unless you mean just the way it was said? Because I will give you the way it is posted on there is pretty funny.
This is P32 HD P36 HP IIRC, the two pitches don't focus the same in direct print.
So pitch is a function of feature size and distance between. Is that focus issue a problem when it is same line width but wider spacing? What about the wider line width identical space between scenario?
Unrelated but...
Funny quirk of GAA. I wonder if the HP cell will be even non Intel products people's go to. Besides the obvious hey the HP cell is more performance than the HD cell, the HP cell can also be the lowest power cell in a GAA world. Because of the variable device widths there is nothing stopping you from using the narrowest nanowire and a high VT gate with the HP cell. And that HP cell due to the larger feature sizes will have less parasitic capacitance. So at that point the HP vs HD cell is really a question of if you want the better power and performance, or even lower per FET cost. When we are talking something like TSMC N3 HD vs HP where the area delta is 0.73x, the gap might not often justify the GAA HP cell. But if the gap is just 0.89x, maybe that is close enough together that the HP cell is the often times the better option. I guess there is also the fact that parts of a die using HP cells should always have lower DD than the HD cell on account of the wider BEOL pitches. So maybe that further sweetens the deal (especially for large die size products)?
They missed AWS? Faraday? Others?
In my recollection, it was merely from the drawing of the HD and HP cells, both appeared to be 5 tracks, and the cell heights are 160 and 180 respectively.
Both size and spacing matter for the pitch dependent best focus.
Yes. It looks like the ecosystem is ready to go on 18A. The test chips are done, the PDk is ready, the ecosystem is ready. Intel 18A seems aligned with TSMC N2 for production starting in 2H 2025. If 18A was a year earlier there would be more customers for sure but in my opinion 18A will be a good test node for Intel Foundry. Intel packaging looks real good. 2026 should be a good year for the foundry business. Still no word on Samsung 2nm but Rapidus 2nm is building ecosystem momentum. It would really be nice to have 3 or 4 options.
I had hoped customers would stand up and say they signed agreements for millions of 18A wafers but that will never happen of course.
"Results may vary."
They talk about enabling direct print, but at the same time the 40-step multipatterning (3 masks) was broadcast widely as well.
3 exposures with many more steps is an odd process integration. This is for 18A node?
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MKWVentures
Moderator
@Daniel Nenni
Intel has great future technologies. agreed. Some questions that I think are more relevant.
1) How many tapeouts of production chips will there be in 2025 and 2026 for external customers on 18A?
2) will there be any external foundry chip shipping in production in 2026?
2) when will external revenue for foundry top $1.2B per year (making intel a top 10 foundry) 2027? 2029? it was $31M last quarter including packaging and wafers.
3) What percentage of customers want BSPD? What percentage are asking for non BSPD?
4) Is 18A cost effective? will operating margins (GAAP) be positive for 18A in 2026
5) I love the UMC partnership. when will the first 12nm products start to ship to customers?
From discussions I had, the only committed customer prioritizing intel is USG. and those are 2030 production.... and low volume (~5K wafer per month total if they deliver).
Is anyone else planning more than 1000 wafers per month in 2026, 2027?
thanks
Intel has great future technologies. agreed. Some questions that I think are more relevant.
1) How many tapeouts of production chips will there be in 2025 and 2026 for external customers on 18A?
2) will there be any external foundry chip shipping in production in 2026?
2) when will external revenue for foundry top $1.2B per year (making intel a top 10 foundry) 2027? 2029? it was $31M last quarter including packaging and wafers.
3) What percentage of customers want BSPD? What percentage are asking for non BSPD?
4) Is 18A cost effective? will operating margins (GAAP) be positive for 18A in 2026
5) I love the UMC partnership. when will the first 12nm products start to ship to customers?
From discussions I had, the only committed customer prioritizing intel is USG. and those are 2030 production.... and low volume (~5K wafer per month total if they deliver).
Is anyone else planning more than 1000 wafers per month in 2026, 2027?
thanks
MKWVentures
Moderator
I think you are underestimating the challenges Intel has financially.
I assume it is for 14A, that was a big focus of this event. 18A is done, 14A is next was the message. This was a Process Technology Innovation Presentation by Dr. Ben Sell. It was a very good presentation, I asked for the slides so I can write about it. Impressive guy.
I think people are underestimating Lip-Bu Tan which I strongly advise against. He really is a wolf in sheep's clothing. The big challenge is resetting the world's expectations of who Intel is and what Intel foundry is really capable of. Pat Gelsinger's overly optimistic foundry messaging did more damage than you might think.
Lip-Bu will meet with customers and do this reset. Unfortunately, the media will continue to bash Intel because that is what they do, that is how they get clicks. I sit with the media at these events, I sit next to the Reuters guys, I hear the same thing they do. The difference is I don't compromise my integrity to get clicks. The difference is they have zero semiconductor experience or education and often have no idea what they are talking about. The real difference is that I give a shit about the semiconductor industry and they do not.
I guess it could be 1 EUV backbone with pitch doubling plus 2 block masks, or SALELE with one block mask? Considering 18A MMP is at 7nm class levels, one would assume 14A is around 5nm class levels due to the modest density uplift over 18A. So I guess those schemes seem plausible.
What is weird about many more steps? Assuming single digit is 9, then 3 exposures should be 27 steps. That leaves 13 steps unaccounted for. But I don't know 13 doesn't sound like a lot once we consider the spacer dep(s), extra hard mask deps, multiple etches to trim spacer or breakthrough the hardmask(s). Other than using 3 exposures instead of 4, the math seems to pass a gut check.
I would assume 14A given the rigid lines definitely some kind of self alingend technique. And Intel has said 18A doesn't use multipatterning for resolution just T2T. Which to me sounds like Intel is doing LELE for those couple of 2 layers. Since Intel is adamant that they are doing direct print for the metal layers and they have shown 1.5D routing enablement I don't think this image can be 18A.
He also got to present his team's work on the Intel 4 VLSI paper back at 2022. Smart man. Cool seeing him move on up to even better things and to get to present on the big stage now. I suspect his list of accomplishments will only continue to grow.
With a direct print at this pitch they won't be able to shrink this layer lengthwise, also due to the tip-to-tip distance.
siliconbruh999
Well-known member
Looking forward to reading it
I thought they presented SALELE with one block mask. Actually, it is usually presented with two block masks, one for each of the two metal line sub-patterns.
I suppose it depends what they count as a "step".
24-32 nm pitch on 0.33 NA is just like 24-30 nm pitch on 0.55 NA. I don't know if the reason for the direct print cutoff is widely understood. It's not dependent on NA.
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