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Intel Foundry Gathers Customers and Partners, Outlines Priorities (Intel Connect Live)

siliconbruh999 said:
Btw I didn't hear a word about turbo cell is it similar to Nanoflex?

View attachment 3125

www.tomshardware.com

Intel details 14A performance and new 'Turbo Cells' that unlock maximum CPU and GPU frequency

I. Am. Speed.
www.tomshardware.com www.tomshardware.com
Click to expand...

Short answer is yes, Intel's response to Nanoflex. You can mix high performance standard cells in with your standard or low power library. I do not remember cell height being mentioned but generally they are a few tracks taller (bigger transistors). Maybe 9 track versus 6 or 5 track? We used to have to choose between a high performance library versus a low power library or something in the middle. Now you can have a mix, tall cells for critical paths and smaller cells for better density/power.

TSMC has been showing N3 FinFlex benchmarks with Arm cores and they really are impressive. Nanoflex is for N2 but same principle. NanoFlex Pro is A14. Everything is on Youtube ;)

 
nghanayem said:
My experience is obviously colored by my experience with leading edge process R&D but I feel that verbage is far too dramatic and sensational for something so routine in manufacturing and in R&D.
Click to expand...

My apologies, I thought you worked in marketing. I will let foundry customers know that their designs will be the same whether they use 14A with or without HNA-EUV. That will be such a relief. :ROFLMAO:
 
Daniel Nenni said:
My apologies, I thought you worked in marketing.
Click to expand...
I'm shocked you thought I was in marketing for these nearly 3 years. Not a dig at marketing people, but I figured the content of my posts and prior comments about my experiences in dry etch, process integration, and in semiconductor manufacturing kind of precluded me from being anything other than a process engineer of some kind.
Daniel Nenni said:
I will let foundry customers know that their designs will be the same whether they use 14A with or without HNA-EUV. That will be such a relief. :ROFLMAO:
Click to expand...
Maybe I am being as dense as a brick and I just don't get the joke, but Intel literally said that at the conference. And I doubt anyone who is working with Intel on 14A would already know that information. Considering TSMC said their plan was for A14P to use high-NA, I have to assume that TSMC's insertion will also be transparent to designers. I doubt they want another N7P vs N7+ situation where you are stuck designing to a non design rule compliant A14 or A14P.
 
nghanayem said:
I'm shocked you thought I was in marketing for these nearly 3 years. Not a dig at marketing people, but I figured the content of my posts and prior comments about my experiences in dry etch, process integration, and in semiconductor manufacturing kind of precluded me from being anything other than a process engineer of some kind.
Click to expand...

I was joking. I'm an admin remember? I see all and know all, kind of like the Wizard of Oz. When did TSMC say their plan was to use HNA-EUV at 14P?
 
Daniel Nenni said:
I attended the previous Intel Foundry event and spoke with Ann K and I remember her saying Intel could do 14A with or without HNA-EUV but the plan was 14A with HNA-EUV. Pat Gelsinger of course was full charge on 14A with HNA and Intel being first.

I did not see Ann at the event this week but this is the first time I have heard Intel say or show on a slide that they would release an EUV version of 14A. To me this is a bad sign for HNA-EUV.

Either way I am with TSMC on this one. HNA-EUV will not be ready for HVM anytime soon. TSMC has the benefit of building a consensus with the top foundry customers around the world and delivering what they decide on. If customers want BSPD TSMC will deliver. The same goes with HNA-EUV but it must pass the cost/risk test set by TSMC's customers.

Just my opinion of course.
Click to expand...
I really believe the only reason that HNA-EUV is being discussed is because Gelsinger made a big deal out of it. If he hadn't tried to use it for bragging rights, it would be a non-issue.
 
Fred Chen said:
So the oft-mentioned 40 steps is for the no High-NA contingency at 14A, then?
Click to expand...
For the previously mentioned reasons from my earlier reply about it, that would be my assumption. Could be wrong, though.
Daniel Nenni said:
I was joking. I'm an admin remember? I see all and know all, kind of like the Wizard of Oz.
Click to expand...
Fair enough. Humor in text form is certainly harder to understand.
Daniel Nenni said:
When did TSMC say their plan was to use HNA-EUV at 14P?
Click to expand...
Apparently Kevin Zhang said it inside this interview linked in this post. This awful internet journalist don't make it clear when they are editorializing, speculating, and saying the words out of people's mouth. So maybe it is a load of BS. Can't read the thing for myself due to the paywall, so I have to rely on the summary that Fansink posted. FWIW an A14P insertion does sound plausible for any layers where there may be benefit. A14 HVM start is about two years after 14A HVM start (assuming Intel starts HVM in early 2027/late 2026 so they can launch 14A products at EOY 2027). By the time we are talking A14P and non Apple customers, we are talking about 3 years after 14A HVM start and 2 years after 14A/14A-E foundry start (assuming Intel sticks to their foundry roadmap) and we'd even be talking about Intel 10A HVM. By then, Intel should have broken high-NA in. If TSMC was to wait for A10 for high-NA, we would be talking about 2031 for first insertion, 5 years after Intel! At that point we might even see something comical like Micron using high-NA for DRAM before TSMC. Waiting that long would be like if Intel first adopted EUV on 18A. I just can't imagine TSMC waiting so long, even if high-NA is nowhere near as ready as Intel makes it out to be.

On a somewhat related note, TSMC extending the time between major processes to 3 years really does make things difficult. You go at the same pace or slower than someone doing 2-year gaps, and you fall behind. You accept the 3-year gaps and try for bigger bangs with each node, and you run the risk of delays. I really think TSMC just needs to have more than 2 leapfrogging process development teams so they can go back to 2-year gaps with the same amount of time as they do now (5 years) for a full process development cycle.
 
nghanayem said:
For the previously mentioned reasons from my earlier reply about it, that would be my assumption. Could be wrong, though.

Fair enough. Humor in text form is certainly harder to understand.

Apparently Kevin Zhang said it inside this interview linked in this post. This awful internet journalist don't make it clear when they are editorializing, speculating, and saying the words out of people's mouth. So maybe it is a load of BS. Can't read the thing for myself due to the paywall, so I have to rely on the summary that Fansink posted. FWIW an A14P insertion does sound plausible for any layers where there may be benefit. A14 HVM start is about two years after 14A HVM start (assuming Intel starts HVM in early 2027/late 2026 so they can launch 14A products at EOY 2027). By the time we are talking A14P and non Apple customers, we are talking about 3 years after 14A HVM start and 2 years after 14A/14A-E foundry start (assuming Intel sticks to their foundry roadmap) and we'd even be talking about Intel 10A HVM. By then, Intel should have broken high-NA in. If TSMC was to wait for A10 for high-NA, we would be talking about 2031 for first insertion, 5 years after Intel! At that point we might even see something comical like Micron using high-NA for DRAM before TSMC. Waiting that long would be like if Intel first adopted EUV on 18A. I just can't imagine TSMC waiting so long, even if high-NA is nowhere near as ready as Intel makes it out to be.
Click to expand...

Why do you think TSMC is not deploying HNA-EUV at A16?
 
fansink said:
If true, it's because it's outside CC Wei's Grand Plan
Click to expand...

Besides, given the odds of the first Panther Lake SKU (4P+8E, 45W) releasing before Christmas, is slimmer than a ghost’s shadow.

CC's already holding a Royal Flush.
 
Daniel Nenni said:
Why do you think TSMC is not deploying HNA-EUV at A16?
Click to expand...
Obviously I wasn't the one who made the decisions. So I can only offer an educated guess. I would lean towards it being because A16 FS interconnects and the devices are the same as the N2 ones. Same fab same equipment. So unless high-NA was ready for HVM in late 2024 (just in time for the N2 transfer from fab12 to fab20) and with fab12 getting their development tools in like 2021 or 2022 (before major N2 integration choices became set in stone); retooling to high-NA after fab20 ramps on N2 or A16 doesn't really make sense. It would be like buying a new car and then selling it in perfect condition 9mo later for a new slightly fancier car. It just doesn't make financial sense. Sort of like why TSMC didn't fully redo 10FF to use EUV or add more EUV layers to N6 beyond the features that TSMC always indented to move to EUV once it was suitable for the applications TSMC identified.
 
nghanayem said:
Obviously I wasn't the one who made the decisions. So I can only offer an educated guess. I would lean towards it being because A16 FS interconnects and the devices are the same as the N2 ones. Same fab same equipment. So unless high-NA was ready for HVM in late 2024 (just in time for the N2 transfer from fab12 to fab20) and with fab12 getting their development tools in like 2021 or 2022 (before major N2 integration choices became set in stone); retooling to high-NA after fab20 ramps on N2 or A16 doesn't really make sense. It would be like buying a new car and then selling it in perfect condition 9mo later for a new slightly fancier car. It just doesn't make financial sense. Sort of like why TSMC didn't fully redo 10FF to use EUV or add more EUV layers to N6 beyond the features that TSMC always indented to move to EUV once it was suitable for the applications TSMC identified.
Click to expand...

I can assure you TSMC was well informed of HNA-EUV being ASML's largest EUV customer. The above decisions were made with full HNA-EUV knowledge, customer input, and a deep risk/reward analysis.

On a higher level, being the front runner TSMC does not have to take risks because honestly they are the only viable foundry for the top semiconductor companies. Intel need not take these risks either to get the NOT TSMC business which should be their focus today. Going all-in on HNA-EUV or any other new technology to try and beat TSMC makes zero sense at this point. That may change of course but today it is all about getting customers to trust what you can deliver and that is not HNA-EUV at this point in time.
 
What is the Base die on Panther Lake? What Process. Is it active. @siliconbruh999 @nghanayem

Some people are claiming base die as a victory on existing parts. I dont think most are even active (Just interconnects or passives). Arrow Lake base is 22nm inactive, correct?

thanks
 
MKWVentures said:
What is the Base die on Panther Lake? What Process. Is it active. @siliconbruh999 @nghanayem

Some people are claiming base die as a victory on existing parts. I dont think most are even active (Just interconnects or passives). Arrow Lake base is 22nm inactive, correct?

thanks
Click to expand...
The base die is 22FFL same as MTL/ARL/LNL it is completely passive here is the leaked schematic for PTL with 12Xe3 GPU From TSMC it matches with what Intel has shown in their foundry event.
Dies are roughly
Compute is 14.28*8.09 115.5252(18 A)
GPU is 6.76*8.09 54.6884 (N3E)
IO is 12.4*3.95 48.98 (N6)
Rest are passive. Thanks to the leakers for leaking info and Intel for confirming the die :ROFLMAO:

Gl4GfEoXwAAsaq9.png
1746546703162.jpeg
 
siliconbruh999 said:
The base die is 22FFL same as MTL/ARL/LNL it is completely passive here is the leaked schematic for PTL with 12Xe3 GPU From TSMC it matches with what Intel has shown in their foundry event.
Dies are roughly
Compute is 14.28*8.09 115.5252(18 A)
GPU is 6.76*8.09 54.6884 (N3E)
IO is 12.4*3.95 48.98 (N6)
Rest are passive. Thanks to the leakers for leaking info and Intel for confirming the die :ROFLMAO:

View attachment 3140View attachment 3141
Click to expand...
great info... is there a SOC die or is it all CPU? where is the NPU? on the CPU GPU or SOC
 
Intel's Arrow Lake processors, officially known as the Core Ultra 200 series, debuted on October 24, 2024, marking a significant advancement in Intel's desktop and mobile CPU offerings.

Is this the first Intel chip with TSMC N3? How well has it done?


Intel's Arrow Lake.jpg
 
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