Intel Foundry Gathers Customers and Partners, Outlines Priorities (Intel Connect Live)

[nghanayem]

I thought they presented SALELE with one block mask. Actually, it is usually presented with two block masks, one for each of the two metal line sub-patterns.

I guess that explains 3 exposures then.

I suppose it depends what they count as a "step".

What would you count as a step? To me anytime you leave a tool for a different tool is a step.

 

[Daniel Nenni]

Daniel Nenni said:
It is interesting to note that Intel will have two versions of 14A, EUV and HNA-EUV.

This news is over a year old. Intel has mentioned that which one they use will depend on which one is better almost a half dozen times at this point. Parallel developments and derisking high risk items were two of the things Ann K said she changed about how Intel does development during interviews she has done over the years.

I do not recall that and I was at the previous event and was briefed by Ann K. Do you have a reference?

Here is a slide from last year:

 

[nghanayem]

Daniel Nenni said:
It is interesting to note that Intel will have two versions of 14A, EUV and HNA-EUV.



I do not recall that and I was at the previous event and was briefed by Ann K. Do you have a reference?

Here is a slide from last year:

View attachment 3121

They have mentioned it on earnings a couple of times when folks were concerned about risk. I think when Ian Curtis interviewed Pat last year Pat mention it. I think Intel discussed it at last SPIE. Lastly they also showed off a completed 14A wafer with test chips last direct connect (which was like 1-2 weeks after Intel got first light on their first tool). It would be impossible for that wafer to be made with highNA proving without a shadow of a doubt there was always a low NA version. After all kind of hard to develop a process without the tools to make it.

 

[MKWVentures]

Daniel Nenni said:
It is interesting to note that Intel will have two versions of 14A, EUV and HNA-EUV.



I do not recall that and I was at the previous event and was briefed by Ann K. Do you have a reference?

Here is a slide from last year:

View attachment 3121

Good input Dan.

there are some great archive documents of what Intel presented. https://newsroom.intel.com/new-technologies/intel-newsroom-archive-2022 (and any other year).

High-NA was hinted at for 18A originally. Then 14A. We will see what actually happens. As Intel Re-orgs all its groups, things will change more.

 

[Daniel Nenni]

They have mentioned it on earnings a couple of times when folks were concerned about risk. I think when Ian Curtis interviewed Pat last year Pat mention it. I think Intel discussed it at last SPIE. Lastly they also showed off a completed 14A wafer with test chips last direct connect (which was like 1-2 weeks after Intel got first light on their first tool). It would be impossible for that wafer to be made with highNA proving without a shadow of a doubt there was always a low NA version. After all kind of hard to develop a process without the tools to make it.

Okay, I heard differently. My take is that Pat Gelsinger wanted to be first on HNA-EUV and he bit off more than he can chew, but that was the original plan, 14A would be HNA-EUV. Intel Fab 62 and 56 in AZ are both HNA-EUV capable. It is a bigger footprint than EUV.

I know Intel has HNA-EUV testing with 18A in OR so maybe those are the wafers we see. There was a display case with wafers at the Intel event but we were not allowed to take pictures or even get too close. There was a security guard chasing people away.

I do know that TSMC has a superior proprietary EUV methodology to what Intel and Samsung have so HNA-EUV will have to improve quite a bit before TSMC uses it for HVM.