I guess that explains 3 exposures then.
What would you count as a step? To me anytime you leave a tool for a different tool is a step.
Intel Foundry Gathers Customers and Partners, Outlines Priorities (Intel Connect Live)
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Daniel Nenni said:
It is interesting to note that Intel will have two versions of 14A, EUV and HNA-EUV.
I do not recall that and I was at the previous event and was briefed by Ann K. Do you have a reference?
Here is a slide from last year:
It is interesting to note that Intel will have two versions of 14A, EUV and HNA-EUV.
I do not recall that and I was at the previous event and was briefed by Ann K. Do you have a reference?
Here is a slide from last year:
They have mentioned it on earnings a couple of times when folks were concerned about risk. I think when Ian Curtis interviewed Pat last year Pat mention it. I think Intel discussed it at last SPIE. Lastly they also showed off a completed 14A wafer with test chips last direct connect (which was like 1-2 weeks after Intel got first light on their first tool). It would be impossible for that wafer to be made with highNA proving without a shadow of a doubt there was always a low NA version. After all kind of hard to develop a process without the tools to make it.
MKWVentures
Moderator
Good input Dan.
there are some great archive documents of what Intel presented. https://newsroom.intel.com/new-technologies/intel-newsroom-archive-2022 (and any other year).
High-NA was hinted at for 18A originally. Then 14A. We will see what actually happens. As Intel Re-orgs all its groups, things will change more.
Okay, I heard differently. My take is that Pat Gelsinger wanted to be first on HNA-EUV and he bit off more than he can chew, but that was the original plan, 14A would be HNA-EUV. Intel Fab 62 and 56 in AZ are both HNA-EUV capable. It is a bigger footprint than EUV.
I know Intel has HNA-EUV testing with 18A in OR so maybe those are the wafers we see. There was a display case with wafers at the Intel event but we were not allowed to take pictures or even get too close. There was a security guard chasing people away.
I do know that TSMC has a superior proprietary EUV methodology to what Intel and Samsung have so HNA-EUV will have to improve quite a bit before TSMC uses it for HVM.
MKWVentures
Moderator
I tell people that 'High NA is not going to win the war'.
For some reason, it was a huge PR effort for Intel with Social media pics on tool delivery like a IG pic of me at a Vegas concert, LOL. [ BTW look for that this weekend!]
I think Both TSMC and Intel will cut it in when it makes the most sense for them. I believe @nghanayem bluntly corrected me when I said High-NA will fit in Arizona Fabs one way or the other.... I got that from Intel Arizona team. Is that true or not?
The new AZ Intel fabs will accommodate HNA-EUV. I confirmed this with Intel. But I doubt HNA-EUV will be in true HVM anytime soon. EUV was very late and it cost Intel dearly. I would hate to see that happen again.
As I mentioned before, the semiconductor industry is very ego driven, Intel probably started it all years ago. Being the first, being the best, blah blah blah. For the foundry business customers determine who is the best. TSMC N3 won by a landslide. TSMC N2 will win by a landslide. It is hard to see TSMC not winning by a landslide at future nodes no matter what Intel Foundry, Samsung Foundry, or Rapidus does. The ecosystem momentum is just too strong. A single digit lead in PPA or being first to anything will just not do it, my opinion.
The good news is that Lip-BU knows this and he will change Intel, absolutely.
I think your overthinking this Dan. high-NA looks to be ready for some kind of insertion in time for 14A. 14A development started before Intel even got their first tool so there needed to be a lowNA version. high-NA comes and Intel says they are happy with the results and continue to say they intend to use it on 14A. But per Ann K's reforms the low-NA track is still being developed in parallel to reduce risk and so that high-NA cannot be responsible for a delay to Intel's first node fully developed from beginning to end as a foundry process technology. It has nothing to do with ego and everything to do with good engeering and risk mitigation. Intel has been bit in the ass too many times by putting all of their eggs in one basket and when things just don't work, intel brute forced the issue to make it work in a suboptimal manner. Abandoning this way of doing things was and still is a great idea.
The same methodology saved TSMC's bacon on 28nm. They developed an SiO2, gate first and a RMG process in parallel. The SiO2 process was on the roadmap first and I think I remember in interviews TSMC originally leaning towards the gate first version of HKMG for 28nm, but when it became apparent that RMG was the only viable option TSMC was able to cancel 32nm gate first and 32nm SiO2. Sometimes initial plans work like a charm EUV, SALELE, metal gate cut, Ru liners, SiGe PMOS fins. Other times they blow up in your face and an alternative needs to be developed non RMG versions of 32/28nm, SAC, self aligned gate end caps. That's just the nature of R&D.
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I attended the previous Intel Foundry event and spoke with Ann K and I remember her saying Intel could do 14A with or without HNA-EUV but the plan was 14A with HNA-EUV. Pat Gelsinger of course was full charge on 14A with HNA and Intel being first.
I did not see Ann at the event this week but this is the first time I have heard Intel say or show on a slide that they would release an EUV version of 14A. To me this is a bad sign for HNA-EUV.
Either way I am with TSMC on this one. HNA-EUV will not be ready for HVM anytime soon. TSMC has the benefit of building a consensus with the top foundry customers around the world and delivering what they decide on. If customers want BSPD TSMC will deliver. The same goes with HNA-EUV but it must pass the cost/risk test set by TSMC's customers.
Just my opinion of course.
siliconbruh999
Well-known member
Btw I didn't hear a word about turbo cell is it similar to Nanoflex?
www.tomshardware.com
Intel details 14A performance and new 'Turbo Cells' that unlock maximum CPU and GPU frequency
I. Am. Speed.
Intel had a special session on the UMC relationship yesterday at Intel HQ. We will cover that shortly.
XtorTourist
Member
Intel bought all of ASML's high NA EUV capacity for 2024 (5-6?). They went big. The clock is ticking on how fast they can make the economics work.
Intel story has stayed consistent on this point.
Pat said the same story as Ann.
They never said that. What they said is they have both with low-NA as a fallback option and that the processes are transparent to designers so Intel can use whatever is best. IMO Intel calling it out again is because arm chair experts keep second guessing Intel about being all in on a technology that isn't make or break. Maybe by mentioning the low-NA version again people will leave the experts to do their jobs. But based on the comments in this thread, I suspect Intel will need to keep repeating that they plan to use high-NA on 14A but have a fallback in case it doesn't work out.
On its own, I don't think so. TSMC having DUV only N7/N7P and an EUV version that could be fully design rule compatible N6 wasn't a bad sign for EUV adoption in 2019/2020.
TSMC is bringing up high NA on a similar schedule to Intel (on 14A generation but also hedging their bets with low-NA). So I don't really understand what you mean here.
Agreed and generally it works. But sometimes customers don't know what would suit them best. See my earlier story I heard about a customer wanting a double patterned 22/20nm to be TSMC like, but then after seeing T20nm they realized that double paterning at the 22/20nm node was not the right PPAC decision so they asked the foundry in question to once again redefine their process to the original minimum metal pitch. I strongly feel mobile AP customers are in the wrong for wanting BSPD to be optional. This is not optional for the best cost per FET scaling or for the eventual move to CFET.
Intel said they just brought up number 2. So no.
No it isn't. Even 6 tools is not a bankrupt the company move. And also Intel said they have a non high-NA fallback. So even if high-NA never becomes viable it doesn't materially change anything.
From what I remember Intel has two, TSMC and Samsung have one each, and the memory makers are still waiting for theirs. I remember ASML saying they can make 10-15 in 2025 if there is demand. I do not remember ASML saying they were sold out or backlogged but I do not follow ASML that closely.
XtorTourist
Member
Digging around, the basis for Intel signing up for 5 high NA EUV purchases in 2024 comes from one rumor source, TheElec. Could easily not be true.
Do you understand what fallback means? It means retreat. It is not a good thing. It is not something people talk about willingly.
I do not know where your information comes from but I was at the conference, I talk to Intel and equipment experts, I talk to big foundry customers and EDA/IP vendors and I will continue to do so. Intel 14A EUV is now on my radar, absolutely.
I think it is smart that Intel is talking openly about Intel 14A EUV because that is what will happen on the foundry side if Intel wants to hit the TSMC A16 design start window. For internal designs I'm sure 14A HNA EUV will be fine, especially since they can opt for TSMC A16 as a fallback.
I will be at CDNLive next week, Lip-Bu and Jensen Huang are keynoting. I will get another pulse on the Intel event and 14A since most of us were there as well.
CadenceLIVE Silicon Valley 2025
cadencelive-sv2025.vfairs.com
fansink
Well-known member
In a fresh development, Intel Corporation's chief commercial officer and general sales manager has announced his resignation. Intel reported the move through an SEC filing earlier today and shared little details behind his departure except for the effective date of the resignation and the reason behind it. According to the firm, the departing executive, Christopher Schell, will resign on June 30th. Intel has yet to announce his replacement, and the departure comes after the new CEO, Lip-Bu Tan, made customer satisfaction a key tenet of his turnaround strategy at Intel.
Intel's Chief Commercial Officer & General Sales Manager Will Leave Company In June
Schell's departure comes after Intel's foundry event in California yesterday, which saw the firm confirm that its leading-edge 18A manufacturing process is on track for delivery in 2025. 18A is Intel's response to TSMC's N2 process technology family, and the Taiwanese firm is expected to start mass production with the new technology in 2025 as well.
Like TSMC, Intel aims to target the contract chip manufacturing market. However, at the foundry event, the firm revealed that the 18A process would be limited to some high-performance computing (HPC) applications. HPC refers to large-scale computing applications such as analytics and AI and uses advanced processors, unlike those found in consumer personal computers.
Intel also revealed a new technology node called the 18A-P. This variant will target general applications, such as consumer chips. It will be available in 2026.
Intel's latest foundry process roadmap. Image: Intel Corporation
Since Intel plans to attract commercial customers to its foundry division, the role of a commerical officer and sales manager will be expanded as well. Previously, the only commercial sales of its products were either to retailers or to businesses using server chips. Intel's manufacturing struggles have also led it to bleed server market share to smaller rival AMD, making the role of a commercial officer even more important.
Customer satisfaction is a key priority of Intel's new CEO Lip-Bu Tan. Immediately after he took over, Tan, in his first message to Intel employees, stressed that the firm's customers were counting on it to execute successfully. By focusing on customer satisfaction, Tan asserted that Intel would, in turn, generate shareholder value.
While its foundry event yesterday was highly anticipated, investors, it seems, are waiting for concrete execution. Intel's shares are down by 3% in morning's trading today. In an analyst note after the event, investment firm Cantor Fitzgerald kept a Neutral rating and a $26 share price target for the firm. Cantor didn't hear "meaningful surprises" at the event, but it was assured by Tan setting "down a market from which [it could] judge performance in the weeks, months, and years ahead." The firm added that concrete details about potential foundry customers, such as NVIDIA and Broadcom, would also be a meaningful development.
Intel's Top Commercial Officer Will Leave In June Says Firm After Key Foundry Event Earlier
Chipmaker Intel's chief commercial officer and general sales manager will leave the firm by June end it says in an SEC filing.
wccftech.com
Edit: yeesh, you asked the same question. But I don’t think anyone has said?Btw I didn't hear a word about turbo cell is it similar to Nanoflex?
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Intel details 14A performance and new 'Turbo Cells' that unlock maximum CPU and GPU frequency
I. Am. Speed.
—
Is this analogous to TSMC’s FinFlex offering?
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My experience is obviously colored by my experience with leading edge process R&D but I feel that verbage is far too dramatic and sensational for something so routine in manufacturing and in R&D.
Having fallbacks is objectively good. It makes delays less likely because you aren't burning the boats behind you. Not having fallback options is how you have Intel 10nm. Having parallel process development is how you have consistent and predictable process node progression like TSMC or Micron. With R&D nothing ever can be taken as a given, so at the end of the day what makes a great R&D team is to dynamicly deal with issues as they come up and find ways to minimize TTM risks.
Your lack of manufacturing experience shows then. In manufacturing and not just semiconductors) you NEVER EVER want to be at the whim of a single point of failure. To be so overconfident to not have contgencies is what would really be a failure.
I mean most of what I said had been said at this conference and in prior information Intel has distributed into the public sphere. That bit about why Intel once again talked about their fallback option if they end up being wrong on highNA, like I said that is just my suspicion because people keep harassing Intel on that topic and saying things that haven't been said or make no common sense. Because otherwise it doesn't make sense to talk about what should be just a footnote for the umpteenth time.
Ouch. While I don't fit into the customer or EDA buckets, but with the rest; you wound me Dan.
If the two versions of the process are completely transparent then foundry ecosystem wouldn't care which version is used. It would be like saying foundry customers won't use a wafer that is made with of N2 that uses Sense.i over Tractus. As long as it can match the PDK criteria with equal or better variation, they couldn't care less if TSMC changed to a newer etcher for a specific application.
That isn't really a fallback since A16 isn't design rule compatible with 14A, A14P, or A14P+BSPDN.