"Results may vary."
They talk about enabling direct print, but at the same time the 40-step multipatterning (3 masks) was broadcast widely as well.
Intel Foundry Gathers Customers and Partners, Outlines Priorities (Intel Connect Live)
- Thread starter Daniel Nenni
- Start date
They talk about enabling direct print, but at the same time the 40-step multipatterning (3 masks) was broadcast widely as well.
Just talking 18A: Microsoft said last year they were signed on to use it. As did Amazon, and according to their website apparently 7 other people signed on (if you also count the USG stuff). Supposedly double-digit adv packaging design wins. Mediatek on i16 for digital TV and WIFI, and a datacenter/edge customer for i3. Apparently Intel is courting the DRAM guys into doing i3 base dies, courting some more i16 customers, and courting a customer who would be interested in co-developing an easier to use i3. Mediatek said today their experience was positive enough to warrant looking into other technologies. BCOM last summer said they were evaluating 18A, and NVIDIA has on multiple occasions in the past expressed interest and said they liked the test chips they had seen (with no process node specified).
What's so funny about that? The exact result is HIGHLY dependent on your process integration choices. To pick two outliers to demonstrate my point. If you choose to have FS only MMP be 40nm, then your FS+BSP vs full BSPDN cost gap will presumably be a lot smaller since the BSPDN "only" process would still be using DUV double patterning for MMP no matter the process. But if you are at 32nm direct print vs 23nm SALELE, yeah that is a night and day difference in cost."Results may vary."
They talk about enabling direct print, but at the same time the 40-step multipatterning (3 masks) was broadcast widely as well.
Unless you mean just the way it was said? Because I will give you the way it is posted on there is pretty funny.
Just viewing it as a kind of disclaimer, looked like fine print to me.What's so funny about that? The exact result is HIGHLY dependent on your process integration choices. To pick two outliers to demonstrate my point. If you choose to have FS only MMP be 40nm, then your FS+BSP vs full BSPDN cost gap will presumably be a lot smaller since the BSPDN "only" process would still be using DUV double patterning for MMP no matter the process. But if you are at 32nm direct print vs 23nm SALELE, yeah that is a night and day difference in cost.
Unless you mean just the way it was said? Because I will give you the way it is posted on there is pretty funny.
This is P32 HD P36 HP IIRC, the two pitches don't focus the same in direct print.
So pitch is a function of feature size and distance between. Is that focus issue a problem when it is same line width but wider spacing? What about the wider line width identical space between scenario?
Unrelated but...
Funny quirk of GAA. I wonder if the HP cell will be even non Intel products people's go to. Besides the obvious hey the HP cell is more performance than the HD cell, the HP cell can also be the lowest power cell in a GAA world. Because of the variable device widths there is nothing stopping you from using the narrowest nanowire and a high VT gate with the HP cell. And that HP cell due to the larger feature sizes will have less parasitic capacitance. So at that point the HP vs HD cell is really a question of if you want the better power and performance, or even lower per FET cost. When we are talking something like TSMC N3 HD vs HP where the area delta is 0.73x, the gap might not often justify the GAA HP cell. But if the gap is just 0.89x, maybe that is close enough together that the HP cell is the often times the better option. I guess there is also the fact that parts of a die using HP cells should always have lower DD than the HD cell on account of the wider BEOL pitches. So maybe that further sweetens the deal (especially for large die size products)?