An Invited Talk at IEDM: Intel’s Mr. Transistor Presents The Incredible Shrinking Transistor – Shattering Perceived Barriers and Forging Ahead

IEDM turned 70 last week. This was cause for much celebration in the form of special events. One such event was a special invited paper on Tuesday afternoon from Intel’s Tahir Ghani, or Mr. Transistor as he is known. Tahir has been driving innovation at Intel for a very long time. He is an eyewitness to the incredible impact of the Moore’s Law exponential and his work has made a measurable impact on the growth of that exponential.

Tahir treated the audience to a colorful perspective on how we’ve arrived at the current level of density and scaling. Pervasive AI will demand substantial improvement in energy efficiency going forward and Tahir took the opportunity to call the industry to action to address these and other challenges as we move toward a trillion-transistor system in package. Here are some of the comments from this invited talk at IDEM as Intel’s Mr. Transistor presents the incredible shrinking transistor – shattering perceived barriers and forging ahead.

About the Presenter

Dr. Tahir Ghani is a senior fellow and director of process pathfinding in Intel’s Technology Research Group. Tahir has a 30-year career at Intel working on many innovations, including strained silicon, high-K metal gate devices, FinFETs, RibbonFETs, and backside power delivery (BSPD), among others. He has filed more than 1,000 patents over his career at Intel and was honored as Intel’s 2022 Inventor of the Year. He has the nickname of “Mr. Transistor” since he’s passionate about keeping Moore’s Law alive.

About the Talk

Besides IEDM turning 70 this year, Moore’s Law will turn 60 next year. Tahir used this milestone to discuss the innovation that has brought us here and what needs to done going forward to maintain Moore’s Law exponential innovation.

Tahir began by discussing a remarkable milestone that lies ahead – one trillion transistors within a package by the end of this decade. He took a sweeping view of the multiple waves of innovation that drove transistor scaling over the last six decades. The graphic at the top of this post presents a view of the journey, from system-on-chip to systems-in-package scaling.  Tahir then presented the key innovations in this journey – past, present and future.

FIRST ERA: 1965 – 2005

The first four decades of Moore’s Law saw exponential growth in transistor count and enabled multiple eras of computing, starting with the mainframe and culminating in the PC. During this time, a second effect called Dennard scaling became important as well as Moore’s Law.

Robert H. Dennard co-authored a now-famous paper for the IEEE Journal of Solid State Circuits in 1974. Dennard and his colleagues observed that as transistors are reduced in size, their power density stays constant. This meant that the total chip power for a given area size stayed the same from process generation to process generation. Given the exponential scaling of transistor density predicted by Moore’s Law, this additional observation provided great promise for faster, cheaper and lower power devices.

Tahir explained that the happy marriage between Moore’s Law and Dennard scaling ushered in something he called the golden era of computing. The era was made possible by numerous innovations in materials and process engineering, most important being the consistent scaling of gate dielectric thickness (Tox) and the development of progressively shallower source/drain (S/D) extensions, which enabled scaling of gate lengths from micron-scale to nanometer-scale while lowering transistor threshold voltage (Vt).

From my point of view, these were the days when semiconductor innovation came from the process teams. If you could get to the next node, you’d have a faster, smaller and lower power product that would sell. Tahir explained that by 2005, power density challenges and the breakdown of Dennard scaling meant it was time for a new approach, which brings us to the present day.

SECOND ERA: 2005 – PRESENT

Tahir explain that during the last 20 years, technologists have shattered multiple seemingly insurmountable barriers to transistor scaling, including perceived limits to dimensional scaling, limits to transistor performance, and limits to Vdd reduction. This era marked the emergence of mobile computing, which shifted the focus of transistor development from raw performance (frequency) to maximizing performance within a fixed power envelope (performance-per-watt).

Many of the innovations from this era in materials and architectures came from Intel. In fact, Tahir has been in the middle of this work for many years. This work expedited the progress of groundbreaking ideas from research to development to high-volume manufacturing. Tahir explained that these innovations ushered in an era of astonishing progress in transistor technology over two decades. He discussed three important innovations from this time.

SEMINAL TRANSISTOR INNOVATIONS

• Mobility enhancement leading to uniaxial strained silicon. In 2004, a novel transistor structure introduced by Intel at the 90nm node incorporated compressive strain for PMOS mobility enhancement. Intel’s uniaxial strain approach was in stark contrast to the biaxial strain approach pursued by the research community and turned out to be superior for performance and manufacturability. Moreover, this architecture proved scalable and enabled progressively higher strain and performance over the years.
• Tox limit leading to Hi-K dielectrics and metal gate electrodes. Intel explored multiple approaches to introduce Hi-K gate dielectrics coupled with metal gate electrodes, including “gate-first,” “replacement-gate,” and even fully-silicided gate electrodes. The replacement metal gate flow adopted by Intel at the 45nm node in 2007 continues to be used in all advanced node processes to this day.
• Planar transistor limits lead to FinFETs. The scaling of the planar transistor finally ran out of steam after five decades, mandating a move to the 3D FinFET

  

  structure. Intel was the first to introduce FinFETs into production at the 22nm node in 2011. Nanometer-scale fin widths enabled superior short-channel effects and, thus, higher performance at lower Vdd. The figure to the right illustrates the evolution of the fin profile over the last 15 years. The 3D structure of fins resulted in a sharp increase in effective transistor width (Zeff) within a given footprint, leading to vastly superior drive currents.

LOOKING AHEAD: THE NEXT DECADE

Tahir made the observation that the seventh decade of Moore’s Law coincides with the emergence of yet another computing era. He pointed out that AI will redefine computing and is already causing a tectonic shift in the enabling silicon platform from general-purpose processors (CPUs) to domain-specific accelerators (GPUs and ASICs).

He went on to say that this shift in computing platform also coincides with another inflection in transistor architecture. By completely wrapping the gate around the channel, the gate-all-around (GAA) transistor is poised to replace the FinFET. GAA transistors deliver enhanced drive current and/or lower capacitance within a given footprint, superior short-channel effects, and a higher packing density. The figure at the right shows what a GAA device looks like in silicon.

Looking ahead, he said the GAA architecture will likely be succeeded by a stacked GAA architecture with N/P transistors stacked upon each other to create more compact, monolithic 3D compute units. Looking further ahead, he explained that 2D transition metal chalcogenide (TMD) films are being investigated as channel material for further Leff scaling, but many issues are still to be addressed.

CALL TO ACTION: NEW TRANSISTOR

Tahir concluded his talk with a sobering observation- worldwide energy demand for AI computing is increasing at an unsustainable pace. Transitioning to chiplet-based system-in-package (SiP) designs with 3D stacked chips and hundreds of billions of transistors per package will increase heat dissipation beyond the limits of current best-in-class materials and architectures. Breaking through this impending “Energy Wall” will require coordinated and focused research toward reducing transistor energy consumption and improving heat removal capability. A focused effort is necessary to develop a new transistor capable of operating at ultra-low Vdd (< 300mV) to improve energy efficiency.

He went on to point out that ultra-low Vdd operation can lead to significant performance loss and increased sensitivity to variability, requiring circuit and system solutions to be more resilient to variation and noise. This suggests the need for a strong collaboration between the device, circuit, and system communities to achieve this important goal. There are many ways to attack this problem.

Tahir reviewed a few, including Tunnel FET (TFET), Negative Capacitance FET (NC-FET), and Ferroelectric FET (FE-FET). All have significant obstacles to overcome. New materials and new structures will need to be explored.

Conclusion

Dr. Tahir Ghani covered a lot of ground in this exceptional review of past, present and future challenges for semiconductor scaling. The best way to end this discussion is with an inspirational quote from Tahir.

“At every significant inflection in the past, when challenges to continued transistor scaling seemed too daunting, technologists across industry and academia forged new paths to enable the arc of exponential progress to continue unabated. There is no reason to believe that this trend will not continue well into the future. There is still plenty of room at the bottom.”

Tahir recently did a Semiconductor Insider’s podcast on SemiWiki. You can hear some of his views in this compelling discussion here. And that’s how Intel’s Mr. Transistor presents the incredible shrinking transistor – shattering perceived barriers and forging ahead.

Also Read:

What is Wrong with Intel?

3D IC Design Ecosystem Panel at #61DAC

Intel’s Gary Patton Shows the Way to a Systems Foundry #61DAC

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