Webinar: Turning Shift-Left from Slogan to Reality
SoC teams are routinely told to “shift left”—to find design and verification problems earlier, where they are cheaper to fix—yet in most flows the first model that is both performance-accurate and authoritative is still the RTL, which arrives late and simulates slowly. This webinar will show that SystemC models built with the open-source MatchLib library and synthesized with Catapult HLS close that gap. Such models exist early, simulate 30x–100x faster than RTL, are throughput-accurate with respect to the final implementation, and are the actual source from which the RTL is generated. Combined with a user-visible scheduling contract backed by formal proofs, they let most design, verification, and architectural exploration move to the source model. The same properties make this flow the natural foundation for the AI-driven design and verification flows now emerging.
What you will learn
- Why “shift left” has stayed a slogan in most SoC flows, and the four things an early model has to deliver before it can change that
- How the usual modeling approaches — spreadsheets, untimed C++, TLM virtual platforms, hand-written RTL — measure up against those four requirements, and where each falls short
- How MatchLib makes a pre-HLS SystemC model tell the truth about system performance, and why throughput accuracy is close enough to cycle accuracy to sign off on
- How to move nearly all functional verification and debug ahead of RTL, reusing the same UVM or SystemC testbenches you will run later on the RTL
- How one model becomes a single source of truth for architects, designers, verification, algorithm, and software teams — and makes architectural exploration and PPA optimization practical along the way
- How teams adopt this step by step alongside existing RTL, and what it looked like on real silicon in NVIDIA’s 87M-transistor ML SoC
- Why this flow is the right foundation for AI-driven design and verification, and how MatchLib is being standardized in the Accellera Synthesis Working Group
Who should attend
- HW Architects and Design Engineers
- HW Design Verification Engineers
- EDA Methodology Engineers
- SoC Design Managers
Speaker:
Stuart Swan
HLS Technologist, Siemens EDA
Stuart Swan is an HLS Technologist in the Catapult team, focusing on SoC modeling for High-Level Synthesis. Prior to Siemens EDA, Stuart worked for Qualcomm and Cadence. Stuart is co-author of the first book on SystemC, “System Design with SystemC,” and was the IEEE technical chairman of the 2005 SystemC LRM. He received his BSEE from Stanford University.
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