Webinar: Integrate Analysis into PCB Design with Sigrity X Aurora

Historically, PCB power distribution networks (PDNs) have been designed based on rules of thumb, such as “put a 0.1uF decoupling cap down for every power pin on the device”. These can lead to more capacitors than necessary, taking up additional space in the layout and driving up cost of the final assembly. In addition, they can lead to an ineffective PDN, where the power ripple requirements of critical devices are not adequately met.

With the shrinking voltage levels, tighter ripple specs, and higher performance in modern ICs, a more methodical approach is needed. Modern analysis and design tools can help enable methodologies to mitigate power integrity problems associated with decoupling caps and AC performance.

This session will discuss these methodologies and demonstrate how analysis and design tools can be used to facilitate them.

Speakers:

Mike Alexander, Application Engineer Architect, Cadence

Host:

Supreeth Mannava, Sr. Principal Product Manager, Cadence

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