Webinar: High-Level Synthesis Summer Hackathon: From Python to High-Performance AI Accelerators
Designing AI inference hardware for edge applications often requires building custom hardware accelerated solutions to meet the demands for ultra-low power consumption and strict real-time response requirements. This webinar introduces Catapult™ AI NN, which provides an automated flow that starts with a Python neural network model and generates an RTL hardware accelerator. The flow enables rapid exploration of design alternatives, helping teams identify the right implementation that best meets their Power, Performance, and Area goals.
You can go beyond just hearing about the technology and put it to work yourself. Join our High-Level Synthesis Summer Hackathon for a hands-on experience building an AI accelerator. Participants will use Catapult AI NN to create the RTL for an AI “Roadside Recognizer,” integrate it into a RISC-V based RTL processor design, verify the complete system, and measure the accelerator’s Power, Performance, and Area.
The winning team will be the one that meets the required performance, accuracy, and area constraints while achieving the lowest energy per inference. Winners will take home valuable prizes and, of course, the glory that comes with building the most energy-efficient design!
What you will learn:
- How to create an RTL hardware accelerator from a Python/ Keras neural network model using Catapult AI NN.
- How to optimize the accelerator implementation through parallelization, pipelining, and resource sharing.
- How to explore architectural alternatives to achieve your PPA goals
- How to target your design to either FPGA or ASIC.
- How to integrate your hardware accelerator into a RISC-V processing sub-system.
Who should attend:
- Hardware designers developing inferencing systems for edge or ultra low-power solutions.
- System architects exploring trade-offs between hardware performance, power, area, and cost.
- Project owners looking to accelerate their hardware design process.
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