Synopsys at DVCon 2016

It’s that time of year again – DVCon starts on Monday Feb 29[SUP]th[/SUP] and as always should be a packed event. Synopsys plans a big showing, in the exhibit hall, in a sponsored lunch, at tutorials and in papers. Time to get your conference shoes on and go check them out – I plan to be there all week.

One of the most obvious things you will notice is Synopsys’ presence in the exhibit hall – they take up a complete side of the hall with stations running the gamut of functional verification: integrated verification solutions, simulation, static analysis, debug, verification IP, emulation and prototyping.

One of the really cool demos is a HAPS integrated FPGA-based prototyping system running an ARC-based processor doing real-time speed sign recognition. If you’re up on advances in ADAS (advanced driver assistance systems), you’ll know that automated recognition systems are a hot topic these days. Come see one working real-time.

The Verification Compiler station will be showing an overview of the functional verification flow including verification engines (such as simulation and formal verification), natively integrated with common verification coverage and with Verdi’s unified debug environment.

On February 23, Synopsys announced an extension to its Verdi debug environment – Verdi Advanced AMS Debug. This is a much-needed development that I’ll certainly be checking out. Mixed-signal analysis gets a lot of press around simulation engines, not so much around debug which is really the heart of getting AMS interfaces right. One of the most commonly cited reasons for respins is problems at these interfaces – improved debug can only help.

The verification IP station will be highlighting Verdi Protocol Analyzer, the protocol and memory aware debug visualization solution and previews the new Protocol Performance Analyzer, offering interactive, transaction and statistical analysis of protocol utilization. You can also check out an overview of the complete library of UVM-based verification IP for Bus, Interface and Memory models.

And of course the SpyGlass station showcases an overview of the SpyGlass RTL signoff solution, including next-generation Lint, Clock / Reset Domain Crossing Analysis, early Power Analysis and optimization.

To help keep you focused (and happy) on this tour through Synopsys verification land – the cocktails featured at the top of this blog (appropriately named “Verification Continuum” cocktails) will be served throughout exhibit hours.

You may also want to consider sticking around for Thursday, or if you have limited time, you might want to consider only attending for Thursday. Synopsys will be featuring a tutorial on developing verification/debug methodologies using VC Apps. This is going to be a can’t-miss tutorial for any verification expert needing to know the latest and greatest tips and tricks to better handle their ever-expanding verification burden.

Afterwards you can break for a relaxing (and free) lunch in the Donner/Siskiyou ballroom and learn how others in your industry are tackling verification complexity and planning for future verification challenges. If you look at DVCon as a way to stay current with verification best practices (and you should), then knowing what other users are doing is an essential part of that picture.

See you there!

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