Antun Domic, on Synopsys’ Secret Sauce in Design

Antun Domic is the GM of the Design Group at Synopsys. I sat down with him a couple of weeks ago.

His name is Croatian although, of course, there was no Croatia back then it was part of Yugoslavia. But in fact he grew up in Chile and went to university there where he studied EE and math. He came to the US as a grad student and did a PhD at MIT in math. He returned to Chile in the Pinochet era and taught for 2 years before returning once and for all to the US (his wife is American). He worked briefly for Honeywell in EDA.

He then went to MIT Lincoln Labs doing work funded by DARPA on restructurable wafer-scale VLSI, big systems larger than chip, essentially silicon compilation. He says DARPA was key in the mid to late 1980s funding EDA research at MIT, Berkely, CMU etc and is probably one key reason why even today EDA is dominated by US companies.

He then moved to the microprocessor group of Digital in the era when every company had internal CAD. I actually interviewed there with his predecessor Alan Hanover, who went on to found Viewlogic. Now part of Synopsys! He left after tapeout of the second Alpha chip and went to Cadence.

At Cadence he ran the group that was doing their synthesis product back then called Synergy. But Synergy had a hard time against Synopsys’ Design Compiler and was eventually canceled (and Cadence bought Ambit where I was VP engineering, but that’s my story not Antun’s). Antun became head of P&R, where Cadence was a lot stronger.

He came to Synopsys in 1997, so nearly 20 years ago, and ran logic synthesis and timing analysis (DC and PrimeTime). Now he has essentially all design tools: logic synthesis, timing, P&R, test, layout verification, circuit simulation and custom layout.

The design environment has changed a lot. 15 years ago everyone designed on node N (whether analog or digital) and was just waiting to move to node N+1. Today there is a much wider spectrum of designs. 90nm for automotive. 28nm will be around for a long time. Obviously lots of stuff on 14/16nm.

A big business imperative for Synopsys is to service 10nm with their leading edge customers (the usual suspects but I won’t mention them since they sometimes get upset about that sort of thing). However, an important part of the industry will remain on established nodes. Some design is still done by hand but most is automated with the usual Verilog, DC, STA, P&R flow. One of the great successes of EDA is the level of automation which is stunning. Today we can do flat P&R of 10M cells, with 10 corners, GHz clocks, FinFET. Design Compiler in the early 1990s was limited to 5K gates.

The focus recently has been introducing ICC2 (Synopsys’ place & route system, called Newton internally). One of the rare occasions that an EDA company looks at the problem completely from scratch: new database, new optimization, new clock-tree synthesis. The only parts kept were placement and routing (which is under 25% of the code).

The main reason for starting from scratch was that you couldn’t just depend on getting increased single thread performance, just more cores. So almost everything needed to be rewritten for threading. Also, existing algorithms don’t always parallelize effectively and so new algorithms are needed to do that. On the horizon was 20/16/14/10 which would need much more speed and data capacity. ICC1 was already the fastest tool available but was still too slow. The plan was for a 5X increase in raw speed. For design planning it ended up 10X faster. There was 5M lines of new code written. Most of the Magma engineering team was retained (despite Magma’s P&R product Talus being phased out) and they contributed to this effort. Other additions were in timing analysis and circuit simulation, for example the current head of PrimeTime was the head of timing analysis at Magma.

Another major project was to take Custom Designer (Synopsys’ internally developed custom design) and Springsoft Laker (acquired, largely confined to Asia). An important project to combine the two technologies has been ongoing. Watch this space for official announcement.

Physical verification, called ICValidator is a much larger business than most people realize. It is used heavily internally in IP development and QA and is now much better supported by foundries. It has been used used to support the largest FinFET designs for many foundries.

The flows have changed. P&R is the tool where a lot of technologies get done today (metal fill, power minimization, chip finishing) and so connecting layout, extraction, verification is very important, such as running DRC/LVS without leaving the P&R environment. Incremental analysis is a big time saver: don’t reextract the whole chip if only a few nets have changed. Synopsys has a big effort in incremental analysis.

Things are much better. 10 years ago there were lots of data transfer format flow issues. Eventually stuff got truly standardized: .lib (aka liberty), LEF/DEF, UPF. Effort now is to make flows incremental and deciding when to do analysis.

Another challenge is teaching algorithms when to give up. When synthesis or P&R can’t make the constraints. Placement has to keep improving too since it is still handling a sea of standard cells but now IP is not just a memory in the corner but perhaps 500-1000 larger blocks spread through the sea. So the cells are no longer “roughly” the same size as with pure standard cells.

His group has about 2000 people distributed everywhere. Even, to his amazement, 70 engineers in his home country Chile.

See also Bijan Kiani Talks Synopsys Custom Layout and More