Multi-Die Systems: The Biggest Disruption in Computing for Years

At the recent Synopsys Users Group Meeting (SNUG) I had the honor of leading a panel of experts on the topic of chiplets. The discussion was based on a report published by the MIT Technology Review Insights in cooperation with Synopsys. This is a very comprehensive report (12 pages) that is available online HERE.

Here is the preface of the MIT paper:

“Multi-die systems define the future of semiconductors” is an MIT Technology Review Insights report sponsored by Synopsys. The report was produced through interviews with technologists, industry analysts, and experts worldwide, as well as a cross-industry poll of executives. Stephanie Walden was the writer for this report, Teresa Elsey was the editor, and Nicola Crepaldi was the publisher. The research is editorially independent, and the views expressed are those of MIT Technology Review Insights. This report draws on a poll of the MIT Technology Review Global Insights Panel, as well as a series of interviews with experts specializing in the semiconductor industry and chip design and manufacturing. Interviews occurred between December 2022 and February 2023.

The focus of a panel like this is the participants. During our lunch prior to the panel I learned quite a bit:

Simon Burke, AMD Senior Fellow, has 25+ years experience building chips starting with HPC vendor Silicon Graphics. He them moved to AMD then to Xilinx and back to AMD through the acquisition. An amazing journey, both depth of knowledge and a great sense of humor. Simon and AMD are leaders in the chiplet race so there was a lot to be learned here.

John Lee, Head of Electronics, Semiconductors and Optics at Ansys, is a serial entrepreneur. I met John when Avant! bought his Signal Integrity company in 1994. Synopsys then bought Avant! In 2002 and John became R&D Director. John then co founded Mojave Design which was acquired by Magma in 2004. John left Magma after they were acquired by Synopsys and later founded Gear Design, a big data platform for chip design, which was acquired by Ansys in 2015.  John is one of my favorite panelists, he says it like it is.

Javier DeLaCruz has 25+ years of experience including a long stint with one of my favorite companies eSilicon. Javier works for Arm handling advanced packaging technology development and architecture adaption including 2.xD and 3D systems. Arm is everywhere so this is a big job.

Francois Piednol is Chief Architect at Mercedes Benz but prior to that he spent 20 years at Intel so he knows stuff. Francios is also a member of UCIe and a jet pilot. He actually owns a jet and as a pilot myself I could not be more impressed. Francios was part of the MIT Chiplets paper mentioned above as well so he is a great resource.

Dr. Henry Sheng, Group Director of R&D in the EDA Group at Synopsys, he currently leads engineering for 3DIC, advanced technology and visualization. He has over 25 years of R&D experience in EDA where he has led development across the spectrum of digital implementation, including placement, routing, optimization, timing, signal integrity and electromigration. He has previously led efforts on EDA enablement and collaborations for emerging silicon technologies nodes. Henry knows EDA.

Dan Kochpatcharin is the Head of Design Infrastructure Management Division at TSMC. Dan is a 30+ year semiconductor professional with 25 years at foundries. For the past 15 years Dan has been instrumental in the creation of the TSMC OIP. Today he leads the OIP Ecosystem Partnerships: 3DFabric Alliance, IP Alliance, EDA Alliance, DCA, Cloud Alliance, and VCA. Dan K, as we call him, knows the foundry business inside and out. I always talk to Dan whenever I can.

Here is the abstract for the panel:

The new era of multi-die systems is an exciting inflection point in the semiconductor industry. From high-performance and hyper-disaggregated compute systems to fully autonomous cars and ultra-high-definition vision systems; multi-die chip designs will transform computing possibilities, driving many new innovations, expanding existing markets and paving the way for new ones. Critical to fueling this momentum is the coherent convergence of innovations across the semiconductor industry by EDA, IP, chiplet, foundry and OSAT leaders. But what’s really happening inside the companies driving what can have one of the biggest impacts on system design and performance in a very long time?

Join this panel of industry leaders who are at the forefront of shaping the multi-die system era. Many have already made the move or are making key contributions to help designers achieve multi-die system success. Listen to their insights, their views on how multi-die system approaches are evolving, and what they see as best practice. Hear about the near, medium, and long-term future for multi-die innovation.

Here are the questions I asked:

Why Multi-Die System and Why Now?

1. Mercedes: What is driving the change, and what is multi-die system offering you?
2. AMD: How do you see the trend to multi-die at AMD and what is the key driver?
3. Synopsys: Are we seeing other markets move in this direction?
4. TSMC: How are you seeing the overall market developing?

It Takes a Village?

1. Arm: How are companies like Arm viewing the multi-die opportunity and how does something like multi-die impact the day-to-day work for designers and system architects working with Arm?
2. Ansys: how is the signoff flow evolving and what is being done to help mitigate the growing signoff complexity challenge?
3. Synopsys: What other industry collaborations, IP, and methodologies are required to address the system-level complexity challenge?

It’s Just the Beginning?

1. TSMC: Which technologies are driving the multi-die growth trend and how do you see these technologies evolving over time?
2. AMD: When do you foresee true 3D – logic-on-logic – entering the arena for AMD and what kind of uplift would if offer compared to infinity fabric style connectivity solutions.
3. Synopsys: How are the EDA design flows and the associated IP evolving and where do customers want to see them go?

Designing Multi-Die Systems?

1. Mercedes: How is the multi-die design challenge being handled at Mercedes and is it evolving in lock-step – true HW/SW co-design – with these ongoing software advancements?
2. AMD: What methodology advancements would you like to see across the industry to make system development more efficient? And what kind of impact does multi-die sytem design have on block designers?
3. Ansys: How is the increased learning curve for these multi-physics effects being addressed?
4. Arm: How is the Arm core design flow evolving to absorb these new degrees of freedom?
5. Synopsys: how is EDA ensuring that designers can achieve the entitlement promised in their move to multi-die?
6. TSMC: How is TSMC working with EDA and OSAT partners to simplify the move to multi-die design?

The Long Term?

1. Mercedes: How is Mercedes approaching the long-term reliability challenge?
2. TSMC: How is TSMC dealing with process reliability and longevity for these expanding use cases?
3. Ansys: What is the customer view of the reliability challenge?
4. Synopsys: Do you see multi-die system as a significant driver for this technology moving forward?

(I can cover the answers to these questions in a second blog)

Summary

The answers to most of the questions are covered in the MIT paper but here are a couple of points that I rang true to me:

Chiplets are truly all about the ecosystem. So many companies could be involved, especially for chip designers that are using commercial chiplets, so where is the accountability? Dan K. made a great point about working with TSMC because they are the ecosystem experts and the buck stops with the wafer manufacturer. The TSMC ecosystem really is like the semiconductor version of Disneyland, the happiest place on earth.

Another point that was made, which was a good reminder for me, is that we are at the beginning of the chiplet era and the semiconductor industry is very fast moving. Either you harness the power of chiplets or the power of chiplets will harness you, my opinion.

Also Read:

Taking the Risk out of Developing Your Own RISC-V Processor with Fast, Architecture-Driven, PPA Optimization

Feeding the Growing Hunger for Bandwidth with High-Speed Ethernet

Takeaways from SNUG 2023

Intel Keynote on Formal a Mind-Stretcher

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