Synopsys at DVCon: tutorial, lunch, keynote, exhibits and more

DVCon is next week, which I’m sure you know already if you are in verification. Of course Synopsys has a rich product portfolio in verification and verification IP (VIP) so is pretty visible at the show.

On Wednesday they are sponsoring lunch. Several Synopsys customers will talk about their view of how the verification landscape is changing. Lunch will be in the Pine/Cedar ballroom from 12.30 onwards. No need to register specially if you are attending DVCon.

Following the lunch, Aart de Geuss, CEO of Synopsys will give the DVCon keynote Systemic Collaboration: Principles for Success in IC Design which looks at the big picture view of how the combination of technology and economics drives everything.

On Thursday, from 1.30 to 3.30 there is a Synopsys tutorial New Levels of Verification IP Productivity for SoC Verification. You need to register here for this if you want to attend. The tutorial is fairly technical and is focused on tnew features added to VIP and how to enable VIP in different environments. There is a demo of debugging at the protocol level (that is, at a much higher level than the actual signals and registers).

Of course Synopsys has a booth in the exhibit hall, number 1105. Exhibits are open 3.30 to 6.30 on Tuesday and 4.30 to 7.00 on Wednesday. You can register for just the exhibits for free.

The main DVCon website is here.

Oh, and while I’m here, Monday evening I’m moderating a panel session Hardware/Software Co-Design from a Software Perspective. All the details are in my earlier blog on the subject here.