WP_Term Object
(
    [term_id] => 159
    [name] => Siemens EDA
    [slug] => siemens-eda
    [term_group] => 0
    [term_taxonomy_id] => 159
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 752
    [filter] => raw
    [cat_ID] => 159
    [category_count] => 752
    [category_description] => 
    [cat_name] => Siemens EDA
    [category_nicename] => siemens-eda
    [category_parent] => 157
)
            
Q2FY24TessentAI 800X100
WP_Term Object
(
    [term_id] => 159
    [name] => Siemens EDA
    [slug] => siemens-eda
    [term_group] => 0
    [term_taxonomy_id] => 159
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 752
    [filter] => raw
    [cat_ID] => 159
    [category_count] => 752
    [category_description] => 
    [cat_name] => Siemens EDA
    [category_nicename] => siemens-eda
    [category_parent] => 157
)

Siemens Hardware-Assisted Verification at the 2024 Design Automation Conference

Siemens Hardware-Assisted Verification at the 2024 Design Automation Conference
by Daniel Nenni on 06-20-2024 at 8:00 am

DAC 2024 Banner

Visitors to Siemens’ booth (#2521) at the 61st Design Automation Conference (DAC) will see on display the Veloce™ CS system that unifies hardware emulation, enterprise prototyping and software prototyping into one hardware-assisted verification and validation platform.

The display will feature the three single-blade system designed for engineering teams to add scalability and capacity as needed: Veloce Strato CS for emulation, Veloce Primo CS for enterprise prototyping, and Veloce proFPGA CS for software prototyping.

The evolution of SoC and system level design made the use of hardware-assisted verification a necessity, an opportunity Siemens embraced. It worked with key customers and partners to develop Veloce CS’ new, fully unified software architecture and innovative hardware built on two highly advanced ICs –– Siemens’ new, purpose-built Crystal accelerator chip for emulation and the AMD Versal™ Premium VP1902 FPGA adaptive SoC for enterprise and software prototyping.

Architected for congruency, speed, and modularity across all three platforms, the Veloce CS system supports design sizes from 40 million gates up to designs integrating more than 40+ billion gates. Veloce CS executes full system workloads with superior visibility and congruency by selecting the right tool for the task, as each task has unique requirements. The result is faster time to project completion and assists in decreasing cost per verification cycle.

Veloce CS system addresses the specific needs of hardware, software and system engineers who play an essential part in delivering the world’s most advanced electronic products by providing the right tool for the task:

  • Veloce Strato CS delivers significant emulation performance improvement over Veloce Strato, up to 5x maintaining full visibility and it scales from 40 million gates (MG) to 40+ billion gates (BG).
  • Veloce Primo CS, based on AMD’s latest Versal Premium VP1902 FPGA, a congruent enterprise prototyping system that scales from 40MG to 40+BG.

Both the Veloce Strato CS and Veloce Primo CS solutions run on the same operating system for congruency while providing the freedom to seamlessly move between platforms. This can dramatically accelerate ramp up, setup time, debug, and workload execution.

  • Veloce proFPGA CS also leverages the AMD Versal Premium VP1902 FPGA-based adaptive SoC, which delivers a fast and comprehensive software prototyping solution, scaling from one FPGA to hundreds. This performance, together with its flexible and modular design, can help engineers accelerate firmware, operating system, application development and system integration tasks.

The entire Veloce CS system is available in a modular blade configuration fully compliant with modern datacenter requirements for easy installation, low power, superior cooling, and compact footprints. Further, the Veloce proFPGA CS solution provides a desktop lab version for additional user flexibility.

General availability of the three hardware platforms is planned for < >2024. Pricing is available upon request. For more information, visit the Siemens website. To arrange a demonstration or private meeting at DAC, send email to

DAC registration is open.

Also Read:

Something new in High Level Synthesis and High Level Verification

3DIC Verification Methodologies for Advanced Semiconductor ICs

Is it time for PCB auto-routing yet?

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