CEO Interview: Anna Fontanelli of MZ Technologies

Anna has more than 25 years of expertise in managing complex R&D organizations and programs, giving birth to a number of innovative EDA technologies. She has pioneered the study and development of several generations of IC and package co-design environments and has held senior positions at leading semiconductor and EDA company including STMicroelectronics and Mentor Graphics.

Tell us about MZ Technologies

MZ Technologies is the marketing brand of Monozukuri S.p.A.  The parent opened for business in Rome, Italy with an initial capital of € 3.5 million in R&D. Since we first opened our doors, our singular focus has been shrinking the time-to-design of complex chiplet and package co-design challenges.  Our mission is to envision, develop and deliver software automated tools and technology that transform the next generation of vertically stacked, modularly packaged integrated circuits designs into commercial successes through superior time-to-market and yield-to-volume efficiencies.

I’m happy to say that we’re making good progress toward achieving the objective we set eight years ago with the introduction of the industry’s first, fully integrated IC/Packing Co-Design EDA tool. To date, we’ve proven the validity of our technology and successfully generated revenue in both Asia and Europe, so now it makes sense for us to bring our expertise to North America.

What problems are you solving?

Great question, and the answer goes directly to our vision.  Simply put, one of the major challenges our customers face is the miniaturization of microelectronics devices. We believe that how society interacts with itself, with technology, and the future will be molded by the Moore’s Law spirit of exponential functional innovation.

To that end, we take on one of the industry’s thorniest problems: Creating the technology design nexus that transforms visions of the future into tomorrow’s innovative IC reality.

What application areas are your strongest?

MZ Technologies delivers innovative, ground-breaking EDA chiplet and package co-design software and methodologies for 2.5D and 3D integrated IC architectures. Our tool, GENIO™, redefines the co-design of next generation heterogeneous microelectronic systems by dramatically improving the automation of integrated silicon and package EDA flows through three-dimensional interconnect optimization.

What keeps your customers up at night?

Let me see if I can explain it this way.

The adoption of 3D stacked silicon architecture demands semiconductor chiplets interconnected with large number (thousands) of I/Os. This translates into higher complexity during the layout engineering phase of a system design, which already accounts for 1/3 of the process from design start to mask layer sign-off. Additionally, the traditional design approach is based on several long and costly design cycles followed by iterative design re-spins before coming to convergence on final product/result. This approach, due to time-to-market limitation, forces the designer to stop at a “good-enough” and usually sub-optimal solution.

Quite a conundrum, no?  Well, where GENIO^TM fits in is that as a holistic design environment spanning across the complete 3D design eco-system, it provides a co-design platform that enables a revolutionary design approach not only putting in communication different design environments (such as IC, Package and PCB) but also empowering the integration with physical implementation tools – physical routers in both space- as well as analysis tools -signal and power integrity and thermal analysis- for physical-aware and simulation-aware 3D system interconnect optimization.

What does the competitive landscape look like and how does MZ Technologies differentiate?

There really isn’t anything like GENIO today, because it was built from the ground-up.  Most of the tools that attempt to do what GENIO does are what we refer to as “bolt-ons.”  In other words, capabilities designed for one function are literally mashed on to another set of capabilities in hopes of overcoming a new set of design challenges.

GENIO, on the other hand, was design and built from the ground-up.  Its system optimization from a unique dedicate cockpit that supports a 3D-aware cross-hierarchical pathfinding algorithm and a rule-based methodology that delivers single-step interconnect optimization throughout the entire 3D system hierarchy.

It’s a chiplet-based system-level architectural exploration that delivers “concept” design phases before physical implementation starts for I/O planning an interconnect optimization that creates and manages the physical relationship and hierarchy between components. And, it uses “what if” analysis and early feasibility studies avoid “dead-end” architecture.

This novel approach creates never-before-seen levels of IC system integration that shorten the

design cycle by two orders of magnitude; drive faster time-to-manufacturing, improve yields, and streamline the entire IC eco-system to enable function- intensive IC-designs that will be the

backbone for the most advanced next-generation integrated circuits. As a result, the optimal system configuration is finally in-reach. It will reduce the overall system design cost dramatically, bringing the “missing piece of the EDA puzzle” needed to complete the 3D-IC design flow.

What new capabilities are you working on?

Today, the commercially available version of GENIO is back-end oriented.  What I mean by that is that it is integrated with and has been validated with physical implementation tools for chiplet-based 3D-stack floor planning that accommodates multiple IP libraries.

The next generation of GENIO will better serve customer requirements by extending the tool’s front-end capabilities for simulation-aware system interconnect optimization and early-on system analysis.  The early-on system analysis capability will be very robust.  It will include state-of-the-art TSV models with R/C electrical performance and mechanical/thermal behavior.  It will also provide thermal modeling based on power dissipation map and TSVs contribution.  Other features will include V&T monitors placement according to identified thermal hotspots and integration with a Hardware-In-the-Loop emulation platform.

How do customers normally engage with MZ Technologies?

Right now, we’re engaging with companies through our representation in Europe and Israel while we open up representation here in North America.  We usually initiate every engagement with an initial presentation and demo of GENIO.  We then move to installing a demon on the customer premises for non-production purposes.  Alternatively, we can run proof-of-concept on customer test cases at our facility.  The final step is annual subscription, full GENIO installation that includes support, maintenance and wiki-like users’ manual and tutorials.

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