WEBINAR: Challenges in analyzing High Performance clocks at 7nm and below process nodes

Proper clock functionality and performance are essential for SoC operation. Static timing analysis (STA) tools have served well for verifying clocks, yet with new advanced process nodes, lower operating voltages, higher clock speeds and higher reliability requirements, STA tools alone can’t perform the kinds of analysis that are needed for clock sign-off anymore. At 7nm and below, a clock failure due to rail-to-rail, duty cycle distortion or aging issues can jeopardize an entire project. To help find and solve these problems San Jose based Infinisim has developed a product called ClockEdge that uses advances in simulation in conjunction with software specifically devoted to analyzing clocks.

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ClockEdge is most relevant for clock speeds in excess of 1GHz and clocks designed at below 10nm process nodes. It can handle traditional clock tree structures and also works with grid, mesh and spine-based clocks. ClockEdge overcomes the limitations that STA encounters, offering deeper insights into clocks that help with performance, power, reliability and more. At advanced process nodes STA tools guard-band their results, leading to over-design and unnecessary power consumption. STA also suffers due to lower operating voltages and non-linear device behavior. Results from STA miss rail-to-rail failures, aging effects and supply induced jitter, all of which can lead to chip failures.

Infinisim’s ClockEdge does more than just look at timing, it ensures that the clock is also functionally correct.  It delivers SPICE accurate results, typically with overnight turnaround even for the largest SOCs. ClockEdge performance is achieved through linear scaling using LSF jobs, unlike multithreading which plateaus at around 10-20X.  ClockEdge analyzes clock performance at multiple PVT corners and will perform HCI and NBTI aging analysis.  Another benefit of ClockEdge is its ability to compute peak-to-peak, average power and leakage current for each gate in the clock.

Unlike STA, ClockEdge analyzes the entire clock domain and looks at every clock path for its timing and electrical analysis at the same time. Going beyond looking at one path at a time can uncover situations where there may be excessive guard-banding or lurking failures. In advanced process node clock designs, duty cycle distortion or asymmetry in high and low pulse widths and rail-to-rail failures are often missed by STA but accurately predicted by ClockEdge. If not detected, both these errors can cause a host of problems and lead to timing problems in the finished chip. ClockEdge does full analog signal analysis to catch and report these issues.

ClockEdge is easy to use because the entire flow is focused on clock analysis. It automatically performs gate level tracing and sensitization, which is followed by transistor level simulation. ClockEdge has comprehensive post processing to generate the reports and the information needed to interpret clock functionality and performance results. As for inputs, ClockEdge uses the same information and data that are used by STA.

Clocks are too important to leave to STA at advanced nodes. A lot needs to be looked at, including power, rail-to-rail and aging to ensure design success. This is especially true for designs below 10nm, where many of these issues can slip through if only STA is used to look at clock issues. Infinisim has put a lot of work into ClockEdge, and they have gained acceptance with major semiconductor companies working on leading edge designs. Their website includes more information on the flow for ClockEdge.

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About Infinisim
Infinisim, Inc is a privately funded EDA company providing design verification solutions. Founded by industry luminaries, the Infinisim team has over 50 years of combined expertise in the area of design and verification.

Infinisim customers are leading edge semiconductor companies and foundries that are designing high-performance mobile, AI, CPU and GPU chips.

Infinisim has helped customers achieve unprecedented levels of confidence in design robustness prior to tape-out. Customers have been able to eliminate silicon re-spins, reduce chip design schedules by weeks and dramatically improve product quality and production yield. www.infinisim.com

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