WEBINAR: Challenges in analyzing High Performance clocks at 7nm and below process nodes

WEBINAR: Challenges in analyzing High Performance clocks at 7nm and below process nodes
by Daniel Nenni on 05-10-2022 at 6:00 am

Clock analysis rail to rail

Proper clock functionality and performance are essential for SoC operation. Static timing analysis (STA) tools have served well for verifying clocks, yet with new advanced process nodes, lower operating voltages, higher clock speeds and higher reliability requirements, STA tools alone can’t perform the kinds of analysis… Read More