Cadence Update on AMS Design and Verification at #55DAC

As a blogger in the EDA industry I get more invitations to meet with folks at DAC than I have time slots, so I have to be a bit selective in who I meet. When the folks at Cadence asked me to sit down and chat with Mladen Nizic I was intrigued because Mladen is so well-known in the AMS language area and he’s one of the authors of, The Mixed-Signal Methodology Guide: Advanced Methodology for AMS IP and SoC Design, Verification, and Implementation. You can buy this book at Amazon for just $115.00 and you’re sure to get a great ROI for the time spent reading it.

Prior to Cadence you find that Mladen worked at both Silvaco and Anacad, so he has a rich history in TCAD and circuit simulation tools.

Q: What are the trends with AMS simulation these days?

For AMS simulators we see that the performance always keep improving, from SPICE-level all the way up to digital. In my recent focus in AMS methodology, we are trying to leverage simulation to do better verification. Verification planning and managing your simulations for analog are now more important, because we need to be smart with simulation.

Model-based verification is becoming mainstream in Mixed-signal. Now with Real Number Modeling in Verilog and System Verilog designers are picking these languages. AMS modeling is a challenge, and it can be approached either top-down or bottom-up.

More engineers are becoming modeling specialists, as they know circuit design, CAD tools and verification approaches. They are asking themselves, what needs to be modeled?

Q: What are the challenges of modeling of AMS blocks?

To accurately model the characteristics of an analog block does require some circuit design understanding, so in most cases it takes a team to create a model, then compare the model against specs or other circuit results.

Q: Have AI or ML techniques been used much for AMS modeling?

ML may provide some help to automate the process of moving a transistor-level netlist up to a behavioral model.

Cadence has templates to help build models more quickly, and the designer needs to know how much detail and accuracy is really needed. It’s the classic benefits versus investment, so don’t over-model and don’t spend too much effort in creating models.

Q: Who on the team should be creating AMS models?

Well, forcing analog designers to do modeling may not work.

Analog designers are changing to adopt modeling in order to meet shorter time to market demands, and there is now more willingness to look at new methodologies.

Q: How should I go about learning AMS modeling?

There are Design Services for learning modeling, plus an IP team can deliver most AMS blocks requested. Training is also available, take a look at the standard courses from Cadence Education Services.

Q: What is happening on the language standards front?

We have both Verilog-AMS and SystemVerilog (getting Extensions to RNM) . Cadence is involved in standards committees and SystemVerilog AMS will become a standard in about 2020 and that process is under IEEE control.

Q: Is cloud-based EDA going to work this time?

In the cloud we see companies mixing and matching their simulation runs, both private and public clouds. Tasks that take the most time fit the cloud model quite well: library characterization, MC, validation or regression. All of the key apps are ready on the cloud today.

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• Cadence’s Smarter and Faster Verification in the Era of Machine Learning, AI and Big Data Analytics Panel
• Cadence in the Cloud