Cadence Update on AMS Design and Verification at #55DAC

Cadence Update on AMS Design and Verification at #55DAC
by Daniel Payne on 08-06-2018 at 12:00 pm

As a blogger in the EDA industry I get more invitations to meet with folks at DAC than I have time slots, so I have to be a bit selective in who I meet. When the folks at Cadence asked me to sit down and chat with Mladen Nizic I was intrigued because Mladen is so well-known in the AMS language area and he’s one of the authors of, The Mixed-SignalRead More


AMS Design, Layout and Verification @ #50DAC

AMS Design, Layout and Verification @ #50DAC
by Daniel Nenni on 05-26-2013 at 9:00 pm


Competition in EDA is absolutely necessary in order for the fabless semiconductor ecosystem to thrive. AMS tools with a low learning curve, high interoperability, and a powerful user interface improve design team productivity and enable a low total cost of ownership. That is why Tanner EDA has shipped over 33,000 licenses of … Read More


USB 3.0 PHY Verification: how to manage AMS IP verification?

USB 3.0 PHY Verification: how to manage AMS IP verification?
by Eric Esteve on 10-18-2011 at 6:38 am

Very interesting question from Zahrein in this thread: “how to manage an embedded USB 3.0 PHY Verification”? To clearly position the problem, Zahrein need to run the RTL verification of a complete SoC integrating an USB 3.0 function, that is the Controller (digital) and the PHY (Analog Mixed Signal) embedded in the SoC. The question,… Read More