What’s New with Circuit Simulation for Cadence?

Every year at DAC I enjoy making the rounds to see what’s new with SPICE circuit simulators, so on June 3rd I met with Xiuya Liand Dan Zhuof Cadence in San Francisco to get an update about their Spectre tool. There’s plenty of competition in the SPICE area from Mentor Graphics (Analog FastSPICE, Eldo, ADiT), Synopsys (HSPICE, CustomSim, FineSim) and others.

Spectre XPS is their transistor-level FastSPICE circuit simulator, and is used to simulate large, full-chip designs including extracted parasitics, even the power-ground network.

Liberate MX – memory cell characterization (from Altos)

Challenges at 20nm and below: there may be more analog blocks, more simulation required for reliability analysis.

Spectre XPS – uses a multi-rate simulation and automatic circuit partitioning, providing about 10x faster simulation results than previous simulators. It’s now easy to trade off between accuracy and speed, by automatically detecting analog blocks which require higher accuracy. The goal is to make this circuit simulator easy to learn and use, with fewer options required to get good results.

There are actually three flavors of Spectre: APS – SPICE engine (single rate, multi-thread), XPS – FastSPICE engine (multi-rate, single thread), RF – frequency analysis.

Types of simulation: Electromigration (EM), Clock, IR Drop.

Previous users of UltraSim can re-use some of their special tuning commands in Spectre XPS.

You can mix and match XPS and APS engines on a design either automatically or manually. Oddly enough this combination is called “mixed-signal” simulation.

Best accuracy is always Spectre APS, then XPS then language modeling. Common inputs and outputs for all Spectre simulators are supported.

Spectre XPS is about 3-13X faster than Spectre APS, depending on the type of circuit. The APS engine takes advantage of multi-cores, while XPS doesn’t support multi-core.

There are many analysis features, like: Safe Operating Area, aging, static analysis, EM, IR, assertions, interactive simulation, dynamic analysis.

You can use PSL and SystemVerilog-based assertions in Spectre. Using Wreal modeling then you can do some automatic checking as UVM mixed-signal. Assertions can help to capture the specifications and design assumptions, document the interfaces and reduce the verification times. PSL and SVA have been extended to transistor-level simulations now. Assertions are placed in a separate file from the Spectre netlist.

Xiuya Li – reviewed the AMS Verification challenges. Recommend using a metric-driven, mixed-signal approach for verification by using: Incisive Enterprise Manager and Planner, Incisive Enterprise Simulator, Virtuoso ADE/AMS Designer.

Digital design and verification methodology is well understood and powerful, while analog design and verification has a diverse methodology instead of a single methodology. Cadence technology for digital is Incisive, analog side is Virtuoso.

On the analog side start adding assertions, use vManager.

In the next release of IC6.1.7 for Virtuoso you can have self-checking verification, instead of brute force waveform processing. Add analog circuit checks – verification IP for analog.

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