Anirudh Keynote at CadenceLIVE 2025 Reveals Millennium M2000

Another content-rich kickoff covering a lot of bases under three main themes: the new Millennium AI supercomputer release, a moonshot towards full autonomy in chip design exploiting agentic AI, and a growing emphasis on digital twins. Cadence President and CEO Anirudh Devgan touched on what is new today, and also market directions beyond EDA and systems design, into physical AI (robots, drones) and sciences AI (molecular design). Jensen Huang (NVIDIA) joined Anirudh for a fireside chat preceding this keynote and Satya Nadella (Microsoft) provided a video endorsement, as did Charlie Kawwas (President of Semiconductor Solutions at Broadcom), reinforcing that Cadence is both serving and partnering with the world leaders in tech.

Millennium M2000 Release

Millennium M2000 is the next generation of the Cadence AI hardware acceleration platform, built on Nvidia Blackwell. For those keeping careful track, Anirudh and Jensen announced this platform in the fireside chat immediately before this keynote but I’m covering it here. Jensen also announced that he is going to buy 10 systems. Quite an endorsement.

I wrote about the first-generation Millennium Enterprise Multiphysics Platform last year, when it was clear it would immediately benefit computational fluid dynamics (CFD). Given how pervasive AI has become throughout the Cadence EDA product line, it is now apparent that Millennium will have an increasing role in chip design.

Hardware acceleration is a fundamental tier in the Cadence strategy, initially for (Boolean) logic simulation but now also in support of numeric simulation, which is where Millennium shines. Accelerating CFD is an obvious application for aerodynamic modeling, datacenter cooling, and hydrodynamic modeling for ships. In biosciences, molecular similarity screening can greatly reduce an initial pool of potential therapies, weeding out candidates with possibly strange behaviors or toxicities, before advancing to more detailed lab testing.

In semiconductor design, Cadence’s Cerebrus Intelligent Chip Explorer has been driving significant improvements in PPA through AI, from chip level to system level using numeric simulation methods, a natural partner with M2000. Other EDA applications in the Cadence tool suite from 3D-IC and packaging design, thermal and signal integrity modeling to analog design and analysis, all benefit from AI which can be further accelerated and scaled on the M2000 system.

A Moonshot to Full Autonomy in Chip Design

Anirudh positions AI advances in EDA following the automotive autonomy SAE model, from levels 1 (basic autonomy) to 5 (full autonomy). Nice analogy and useful to grade progress. Cadence started building their JedAI platform more than 5 years ago, to centralize data from spec through to manufacturing as a mechanism to support generative AI throughout the design cycle and across designs. Now AI is a daily reality in design flows they support, to the point that he feels much of what they offer is already at levels 2 or 3. Advances he announced in this talk stretch to levels 3 and 4, thanks in part to a big investment in agentic AI which makes more complex chains of reasoning possible.

Level 5 – full autonomy – he acknowledges is a moonshot but like all moonshots worth attempting to see how far they can get. They can advance on multiple fronts. RTL generation in part, maybe through a CoPilot type of approach (assisted generation with RAG). Partly through leveraging proven IP – Cadence now has a rapidly growing IP catalog to support this direction. Partly through AI-generated C, for which Cadence can use their proven C to RTL technologies. Also partly through generating testbenches, both UVM and Perspec. The following keynote from Uri Frank at Google touched on joint work between Cadence and Google in this area.

On leveraging proven IP, Cadence continues to invest significantly in growing their own IP catalog. Anirudh mentioned this area now has one of the biggest R&D teams in the company and an expanding portfolio across protocol IP and compute IP, including their Tensilica family and NPUs and their recent NeuroEdge introduction (on which I will write more in a following blog). They also recently announced their intent to acquire Secure-IC, a well-respected company in all areas of hardware security, from design to deployment and eventual decommissioning (I wrote about them recently).

Now Agentic AI is available in Integrity 3D-IC, Cerebrus AI Studio and Virtuoso Studio. I’m looking forward to seeing applications in functional verification – maybe next year?

Continued Focus on Digital Twins

In semiconductor design digital twins are a way of life. A critical component here is hardware-assisted logic verification. Last year customers added almost 460 billion gates in new Palladium/Protium capacity, easy to understand when you consider the sizes of designs, particularly AI designs, that are being built today around the world. It’s also not surprising to learn that the Palladium emulation platform, built on a Cadence designed custom chip, is itself pacing those design sizes at 120 billion transistors per chip, 16 trillion transistors in a rack. A super-sized chip to verify super-sized chips!

Beyond semiconductor design, in the physical and bio world digital twins are less widely used, in part because it is more difficult to capture all the complexity of the mechanical, chemical and ambient constraints that must go along with that modeling. Difficult but becoming more approachable thanks to AI, agentic AI, and AI hardware accelerators.

One area that is advancing quite rapidly is in digital twins for datacenters. The Cadence Reality Digital Twin Platform is becoming a reality (😀) for datacenter design and upgrades, where the cost of power and cooling is an everyday headline topic given the growing volume of AI accelerator hardware. Thermal modeling depends critically on very detailed analysis and recommendations to manage thermal hot spots and cooling flows, whether ambient, forced air, or liquid. Rack placements, cooling unit placements, vent placements all depend on optimized modeling. AI to mitigate the impact of AI on power – physician heal thyself indeed. Cadence is closely partnered here with Nvidia.

Digital twins are becoming equally important for aircraft design, drone design (now pervasive in many applications) and robot design for automated factories, warehouses, hospital logistics support. And continuing of course for design of cars, trucks and other transportation options. Semiconductors and systems supporting these use cases will have much tighter power envelopes and significantly more mixed signal content to support all the sensors these systems require, playing nicely to Cadence strengths from chip design up through system design.

Big picture views, hot AI investment, focus on growing markets in tech and partnering with tech leaders on system-level applications. Looks promising to me!