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Cadence @ #51DAC Must See!

Cadence @ #51DAC Must See!
by Daniel Nenni on 05-13-2014 at 3:00 pm

Cadence is excited to bring a full slate of demos, technical presentations, papers, and more to the Design Automation Conference (DAC) June 1-5, 2014, in San Francisco, CA. From our technical experts, you’ll learn tips and techniques from areas including low power, mixed signal, advanced nodes, signoff, verification, and IP, to name just a few. Get details.

First and foremost the food events:

Cadence, our customers, and our partners will share their expertise and experiences in electronic design during panels and presentations throughout DAC. The luncheons/breakfast will be held in Room 104 at the Moscone Center, which is located in front of Exhibit Hall B.

REGISTER HERE!

Monday, June 02, 2014

LUNCHEON: Extending Mixed-Signal Power Management Verification to RTL
12:00 PM – 01:30 PM
We live in an analog world fueled by digital speed and bandwidth and brought to the masses through advanced-node miniaturization. Throw into this mix the ever-growing appetite for energy efficiency, and you’ve got yourself a serious challenge with mixed-signal functional and power management verification. Come to our luncheon session to learn how your colleagues are dealing with these growing verification challenges. Find out about new methodologies and techniques being developed to keep you a step ahead of tapeout failure nightmare.

Tuesday, June 03, 2014

BREAKFAST: The Shift to Software-Driven Verification
08:00 AM – 09:30 AM
Waiting too long to integrate hardware and software has proven to have disastrous results. The development, integration, and verification of complex hardware/software systems is demanding a “shift-left” into the pre-silicon phase of tasks that traditionally have been done after silicon has become available. From the early stage of transaction-level modeling- (TLM-) based development through RTL-based development, software has become an important part of the verification process. This session will introduce the challenges design teams are facing. The speakers will also discuss some key user experiences on how verification is shifting and how EDA tools are enabling that shift.

LUNCHEON: High-Speed Cross-Fabric Interface Design: It’s Not 1’s and 0’s Anymore, It’s a Noisy World
12:00 PM – 01:30 PM
It’s all of the above. That’s the answer to the question of why high-speed digital design is becoming a mainstream topic. Previously reserved for those on the edge of process, materials, architecture, and methodologies, the complex effects are now being felt by more and more design teams as the power and performance envelope gets tighter and tighter. Digital design merges with analog, and divide and conquer breaks down. Cross-fabric analysis (chip-package-board) is already a necessity. Prediction: design practices will have to shift to “co-design” and “in-design” techniques to solve the complex iteration and closure issues. Come hear a panel of experts share their experiences and their thoughts on what else is needed and what might be in store in the future for high-speed digital design.

Wednesday, June 04, 2014


LUNCHEON: How High-Performance Digital Design Enables a Paradigm Shift in the Enterprise Datacenter
12:00 PM – 01:30 PM
Next-generation, 64-bit server architecture-based SoCs are at the dawn of an exciting inflection point in the networking and cloud-computing industry. The landscape is rapidly shifting as these new SoCs aim to meet the scalable-performance and energy-efficiency requirements of the evolving enterprise datacenter workload. The ecosystem partnership on processor core and physical IP, EDA RTL-to-signoff tools, and advanced foundry process is critical for success. Come hear from our esteemed panelists about what is taking place in the industry to help next-gen 64-bit technology deliver high performance at higher efficiency than traditional processor offerings. Understand the techniques used for handling the increased complexity of larger IP cores and design closure at advanced 16nm nodes. Learn about design planning for optimized floorplans, physically aware synthesis, and the use of route-driven optimization, clock-concurrent design, and massively parallel signoff technology to improve performance and power efficiencies. Come listen to how you can mitigate risk and improve time to market by getting a head start on designing your next-generation, 64-bit server architecture-based SoCs.

At Cadence® DAC Technology Sessions, you’ll get in-depth presentations and demonstrations of our technologies and methodologies for developing the highest quality silicon, systems-on-chip, and complete systems at lower costs. Session options include our latest solutions in the areas of signoff, mixed signal, low power, RTL-to-GDSII, custom, functional verification, verification IP, system development and hardware-software integration, high-level synthesis, and IC packaging.

REGISTER HERE

[TABLE] border=”1″ cellpadding=”5″ style=”margin-top: 5px; border-collapse: collapse”
|-
| valign=”top” style=”width: 80px” | June 2, 2014
| align=”center” valign=”top” style=”font-weight: bold; background-color: #dedede” | Suite 1
| align=”center” valign=”top” style=”font-weight: bold; background-color: #dedede” | Suite 2
|-
| style=”font-weight: bold; background-color: #dedede” | 10:00 AM
| valign=”top” style=”width: 300pxpx” | Benefits of Mixed-Signal, Open Access, Interoperable Flow
| valign=”top” style=”width: 300pxpx” | Using Virtuoso Space-Based Router for Pin-to-Trunk Routing
|-
| style=”font-weight: bold; background-color: #dedede” | 11:00 AM
| valign=”top” style=”width: 300pxpx” | Fast and Accurate Signoff Extraction for Advanced Nodes
| valign=”top” style=”width: 300pxpx” | Characterization for Advanced Nodes
|-
| style=”font-weight: bold; background-color: #dedede” | 12:00 PM
| valign=”top” style=”width: 300pxpx” | Tackling the Most Difficult ECOs with ‘Congestion and Timing Smarts’
| valign=”top” style=”width: 300pxpx” | Electrically Aware Design: Addressing the Productivity Gap in Analog Design
|-
| style=”font-weight: bold; background-color: #dedede” | 01:00 PM
| valign=”top” style=”width: 300pxpx” | RTL Design in a Physical World: Synthesis and Test
| valign=”top” width=”300px” | High-Level Synthesis Improves Time to Market, Quality of Results, and IP Reuse
|-
| style=”font-weight: bold; background-color: #dedede” | 02:00 PM
| valign=”top” width=”300px” | DDR4 Signoff: Chip-Package-Board IO-SSO Analysis
| valign=”top” width=”300px” | Full Custom and Analog Advanced Node Design
|-
| style=”font-weight: bold; background-color: #dedede” | 03:00 PM
| valign=”top” width=”300px” | Scalable Timing and Power Signoff Analysis with Tempus and Voltus Solutions
| valign=”top” width=”300px” | Incisive Verification Apps: Automated Formal Solutions for Common Verification Issues
|-
| style=”font-weight: bold; background-color: #dedede” | 04:00 PM
| valign=”top” width=”300px” | Advanced Mixed-Signal Verification Methodologies for ICs and SoCs
| valign=”top” width=”300px” | SimVision and Incisive Debug Analyzer Reduce Debug Time from Days to Minutes
|-
| style=”font-weight: bold; background-color: #dedede” | 05:00 PM
| valign=”top” width=”300px” |
| valign=”top” width=”300px” | Accelerating Embedded Software Development with Cadence Rapid Prototyping Platform
|-

[TABLE] style=”width: 100%”
|-
| style=”width: 100%” | [TABLE] border=”1″ cellpadding=”5″ style=”margin-top: 5px; border-collapse: collapse”
|-
| valign=”top” style=”width: 80px” | June 3, 2014
| align=”center” valign=”top” style=”font-weight: bold; background-color: #dedede” | Suite 1
| align=”center” valign=”top” style=”font-weight: bold; background-color: #dedede” | Suite 2
|-
| style=”font-weight: bold; background-color: #dedede” | 10:00 AM
| valign=”top” style=”width: 300pxpx” | System Interconnect Planning to Optimize Cross-Fabric Integration for Cost and Performance
| valign=”top” style=”width: 300pxpx” | Full Custom and Analog Advanced Node Design
|-
| style=”font-weight: bold; background-color: #dedede” | 11:00 AM
| valign=”top” style=”width: 300pxpx” | Scalable Timing and Power Signoff Analysis with Tempus and Voltus Solutions
| valign=”top” style=”width: 300pxpx” | Incisive Verification Apps: Automated Formal Solutions for Common Verification Issues
|-
| style=”font-weight: bold; background-color: #dedede” | 12:00 PM
| valign=”top” style=”width: 300pxpx” | High-Performance, Advanced-Node Encounter Digital Implementation
| valign=”top” style=”width: 300pxpx” | SimVision and Incisive Debug Analyzer Reduce Debug Time from Days to Minutes
|-
| style=”font-weight: bold; background-color: #dedede” | 01:00 PM
| valign=”top” style=”width: 300pxpx” | Foundry Qualified, Comprehensive Physical Signoff (Physical Verification and DFM) and Optimization f
| valign=”top” width=”300px” | ARM v7 and v8 Based Accelerated System Development
|-
| style=”font-weight: bold; background-color: #dedede” | 02:00 PM
| valign=”top” width=”300px” | DDR4 Signoff: Chip-Package-Board IO-SSO Analysis
| valign=”top” width=”300px” | Spectre Simulation Technology – Addressing the Challenges of Advanced Node Design
|-
| style=”font-weight: bold; background-color: #dedede” | 03:00 PM
| valign=”top” width=”300px” | Benefits of Mixed-Signal, Open Access, Interoperable Flow
| valign=”top” width=”300px” | Electrically Aware Design: Addressing the Productivity Gap in Analog Design
|-
| style=”font-weight: bold; background-color: #dedede” | 04:00 PM
| valign=”top” width=”300px” | Comprehensive Low-Power Solution – A Must for Today’s Complex Power-Managed Designs
| valign=”top” width=”300px” | Metric-Driven Verification from IP to SoC with Incisive vManager Solution
|-
| style=”font-weight: bold; background-color: #dedede” | 05:00 PM
| valign=”top” width=”300px” | RTL Design in a Physical World: Synthesis and Test
| valign=”top” width=”300px” | What’s New with the Palladium XP Series
|-

|-

[TABLE] border=”1″ cellpadding=”5″ style=”margin-top: 5px; border-collapse: collapse”
|-
| valign=”top” style=”width: 80px” | June 4, 2014
| align=”center” valign=”top” style=”font-weight: bold; background-color: #dedede” | Suite 1
| align=”center” valign=”top” style=”font-weight: bold; background-color: #dedede” | Suite 2
|-
| style=”font-weight: bold; background-color: #dedede” | 10:00 AM
| valign=”top” style=”width: 300pxpx” | Comprehensive Low-Power Solution – A Must for Today’s Complex Power-Managed Designs
| valign=”top” style=”width: 300pxpx” | Metric-Driven Verification from IP to SoC with Incisive vManager Solution
|-
| style=”font-weight: bold; background-color: #dedede” | 11:00 AM
| valign=”top” style=”width: 300pxpx” | Tackling the Most Difficult ECOs with ‘Congestion and Timing Smarts’
| valign=”top” style=”width: 300pxpx” | ARM v7 and v8 Based Accelerated System Development
|-
| style=”font-weight: bold; background-color: #dedede” | 12:00 PM
| valign=”top” style=”width: 300pxpx” | Advanced Mixed-Signal Verification Methodologies for ICs and SoCs
| valign=”top” style=”width: 300pxpx” | Using Virtuoso Space-Based Router for Pin-to-Trunk Routing
|-
| style=”font-weight: bold; background-color: #dedede” | 01:00 PM
| valign=”top” style=”width: 300pxpx” | Scalable Timing and Power Signoff Analysis with Tempus and Voltus Solutions
| valign=”top” width=”300px” | What’s New with the Palladium XP Series
|-
| style=”font-weight: bold; background-color: #dedede” | 02:00 PM
| valign=”top” width=”300px” | High-Performance, Advanced-Node Encounter Digital Implementation
| valign=”top” width=”300px” | Characterization for Advanced Nodes
|-
| style=”font-weight: bold; background-color: #dedede” | 03:00 PM
| valign=”top” width=”300px” | System Interconnect Planning to Optimize Cross-Fabric Integration for Cost and Performance
| valign=”top” width=”300px” | High-Level Synthesis Improves Time to Market, Quality of Results, and IP Reuse
|-
| style=”font-weight: bold; background-color: #dedede” | 04:00 PM
| valign=”top” width=”300px” | Foundry Qualified, Comprehensive Physical Signoff (Physical Verification and DFM) and Optimization f
| valign=”top” width=”300px” | Accelerating Embedded Software Development with Cadence Rapid Prototyping Platform
|-
| style=”font-weight: bold; background-color: #dedede” | 05:00 PM
| valign=”top” width=”300px” |
| valign=”top” width=”300px” | Spectre Simulation Technology – Addressing the Challenges of Advanced Node Design
|-

 And the best for last:

Mix, Mingle, and Enjoy!

Ready to party? Mix, mingle, and have a fun time with your peers at the popular Denali Party by Cadence.

For your musical entertainment, Disco Inferno will be back to rock the house. And this year, we’ll kick off the night with “Rockstar Karaoke” — your chance to sing with a live band and be the rock star you’ve always wanted to be! Sign up and select your song for Rockstar Karaoke via your registration form. We’ll let you know by email if you’ve been selected to participate.

Didn’t make the Rockstar Karaoke cut? Don’t worry, you can still sing your heart out at the karaoke room at Slide, next door to Ruby Skye.

We look forward to hanging out with you at the Denali Party!

NOTE: You must pick up your wristband at the Cadence booth (#2610) before noon on Tuesday, June 3 or your reservation will be given to another guest.

REGISTER HERE

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