Front-End Design Summit: Physically Aware Design

Save closure time and boost performance by incorporating knowledge of physically aware design early into your front-end design implementation flow

With the adoption of advanced process nodes, design closure is becoming increasingly difficult due to the lack of convergence between the front end and the back end of the register-transfer level (RTL)-to-signoff flow. Incorporating knowledge of physically aware design early in the front-end design process is quickly becoming a must-have to enable faster convergence in the back end.

Join us at the Front-End Design Summit, where you can network with fellow logic designers and speak directly with Cadence® R&D experts from our Encounter® RTL Compiler, Encounter® Test, and Conformal® product teams. At this day-long technical event, you will:

• Hear from Cadence customers the challenges they faced during logic synthesis, advanced low-power design and verification, engineering change order (ECO), and design-for-test (DFT) implementation, and the strategies they employed to address them
• Discover how best to achieve power, performance, and area goals on industry-leading IP cores
• Network, share your knowledge, and exchange best practices with your industry peers
• Hear from Cadence R&D on product updates, solutions, and future directions

Date: 05 Dec 2013 (9:00am – 5:00pm PST)
Location:Cadence Design Systems Campus, Bldg. 10 , San Jose, CA

Agenda
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| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; background: #eee; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Time
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; background: #eee; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Title
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; background: #eee; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Speaker
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| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | 9:00am
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Registration and Breakfast
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” |
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| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | 9:30am
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Welcome
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Andy Lin, VP of R&D, Front End Design, Cadence
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| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | 9:45am
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Keynote
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| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | 10:15am
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Advantages of RTL Compiler Using Physically Aware Structuring
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Jaga Shanmugavadivelu, Techincal Lead, Cisco Systems
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| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | 10:45am
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Break
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” |
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| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | 11:00am
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Addressing Physical Challenges Early in RTL Synthesis
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Ankush Sood, R&D Director, Cadence
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| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | 11:30am
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | ECO Experience on a High Performance Mobile ASIC
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Deepa Thali, Staff Engineer, Qualcomm
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| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | 12:00pm
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Corporate Update
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Chi-Ping Hsu, Sr. VP R&D, DSG and CSO, Cadence
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| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | 12:15pm
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Lunch with R&D
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| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | 1:15pm
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Optimizing PPA for Tensilica BBE32 Core
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Jagesh Sanghavi, Engg. Director, Cadence
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| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | 1:45pm
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Power-Efficient SmartScan Test Architecture for Processor Designs
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Alan Hales, DFT Lead, Texas Instruments
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| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | 2:15pm
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Addressing Test Challenges for GigaScale SoCs
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Michael Vachon, Group Director R&D, Cadence
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| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | 2:45pm
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Break
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” |
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| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | 3:00pm
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Comparison of Various Flows for Post-Mask ECO: Manual vs. Conformal-ECO
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Pihay Saelieo, Senior MTS CAD Design Engineer, Spansion
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| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | 3:30pm
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Streamlining Your Verification Flow
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Kei-Yong Khoo, Group Director R&D, Cadence
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| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | 4:00pm
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Bridging the Gap in an RTL2GSDII Flow
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Paul Cunningham, VP of R&D, ICD, Cadence
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| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | 4:30pm
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Final Q&A and Conference Survey
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” |
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| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | 4:45pm
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Networking Event, iPad Mini Drawing
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