Manage your IC’s Stress for right performance

As we have moved towards lower process nodes to improve performance of ICs with higher density and functionality, many manufacturing effects have appeared which can render ICs useless, even though the layout design could be correct as per traditional design rules. What is more worrisome is the variability of these effects which depend on the proximity and surrounding of actual layout elements and hence is unpredictable before the layout is done. Actual layout needs to be considered to analyze these effects and action taken before final layout to keep the manufacturing abstraction level at the layout stage.

Variability due to Stress is a very prominent such effect which can significantly impact timing closure of the design. Timing characteristics from the standard cell characterization data no longer remain valid. Stress can also be induced intentionally in order to improve electron (for NMOS) and hole (for PMOS) mobility which can improve the drive current leading to higher performance. Unintentional stress is the manifestation of STI (Shallow Trench Isolation) and WPE (Well Proximity Effect). STI specifically depends on proximity of transistors in the layout and LOD (length of diffusion). Effects of these could be positive (if not negative) on the performance but that is unpredictable and cannot be relied upon. A typical example below shows how Isat current of NMOS and PMOS degrades with closer surrounding Poly –

Hence, Stress whether intentional or unintentional, needs to be modelled appropriately where current changes due to transistor structure and its surrounding geometry sizes such as well boundaries are captured and applied to produce a design layout which can result in correct working IC with intended performance.

Cadence, as being always innovative, provides a comprehensive solution for modelling and mitigating Stress induced variability at standard cell library development phase as well as post-route layout phase. A complete detail about the Stress, its impact and how Cadence tools handle those is given in its white paper at –
Modeling Stress-Induced Variability Optimizes IC Timing Performance White Paper

Cadence’s Litho Electrical Analyzer, Litho Physical Analyzer, Physical Verification and QRC Extraction tools provide an environment which can analyze standard cell library for variability over a number of different layout contexts and provide metrics (such as litho hotspots, gate variation, delay variation and leakage variation) for library designers to take corrective actions and for P&R tools (Cadence’s EDI system) to mitigate placement induced variability.

The extraction results are very robust as they take into account mobility, saturation velocity and threshold voltage parameters. The designer can optimize library in best possible manner as per architectural and layout tradeoffs.

Post-layout variability analysis can be done by both library designers and chip designers. Chip designers can use Litho Electrical Analyzer along with Encounter Timing System to identify, analyze and optimize the critical paths which may be sensitive to proximity effects.

[1 – flow for library designers, 2 – flow for chip designers]

Traditionally at higher process nodes sensitive circuitry is protected by using guard bands, but that is no more useful as Stress induced timing variations have become more pronounced at lower nodes. Tools for actual Litho analysis are needed to detect variation hot spots and manage them by adjusting the layout appropriately for the manufacturing success. Cadence provides an apt environment with specific tools for the same.