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Cadence
Posted on by Daniel Nenni

Addressing the Nanometer Custom IC Design Challenges! (Webinars)

Addressing the Nanometer Custom IC Design Challenges! (Webinars)
by Daniel Nenni on 07-26-2012 at 7:30 am
Categories: Cadence, EDA

Selectively automating non-critical aspects of custom IC design allows engineers to focus on precision-crafting their designs. Cadence circuit design solutions enable fast and accurate entry of design concepts, which includes managing design intent in a way that flows naturally in the schematic. Using this advanced, parasitic-aware environment, you can abstract and visualize the many interdependencies of an analog, RF, or mixed-signal design to understand and determine their effects on circuit performance.

Watch technical presentations and demonstrations on-demand and learn how to overcome your design challenges with the latest capabilities in Cadence custom/analog design solutions.

Virtuoso 6.1.5 – Front-End Design
Steve Lewis, Product Marketing Director
Highlights of new front-end design tools and features (including a new waveform viewer, Virtuoso Schematic Editor, and Virtuoso Analog Design Environment), and how to identify and analyze parasitic effects early.
View Sessions

Virtuoso Multi-Mode Simulation
John Pierce, Product Marketing Director
Updates on the latest simulation capabilities including Virtuoso Accelerated Parallel Simulator distributed multi-core simulation mode for peak performance; a high-performance EMIR flow; Virtuoso APS Accelerated Parallel Simulator RF analyses; and an enhanced reliability analysis flow.
View Sessions

Virtuoso 6.1.5 – Top-Down AMS Design and Verification
John Pierce, Product Marketing Director View Session
Highlights of the latest in advanced mixed-signal verification methodology, checkboard analysis, assertions, and how to travel seamlessly among all levels of abstraction of the design.
View Sessions

Virtuoso 6.1.5 – Back-End Design
Steve Lewis, Product Marketing Director View Session
Highlights of the latest in constraint-driven design; Virtuoso Layout Suite; links between parasitic-aware design, rapid analog prototyping, and QRC Extraction; and top-down physical design: floorplanning, pin optimization, and chip assembly routing with Virtuoso Spaced-Based Router.
View Sessions

Virtuoso 6.1.5 – MS Design Implementation
Michael Linnik, Sr. Sales Technical Leader View Session
Highlights of the latest mixed-signal implementation challenges and solutions that link Virtuoso and Encounter technologies on the OpenAccess database, including analog/digital data interoperability, common mixed-signal design intent, advances in design abstraction, concurrent floorplanning, mixed-signal routing, and late-stage ECOs.
View Sessions

What’s New in Signoff
Hitendra Divecha, Sr. Product Marketing Manager
Highlights of standalone and qualified in-design signoff engines for parasitic extraction, physical verification, power-rail integrity analysis, litho hotspot analysis, and chemical-mechanical polishing (CMP) analysis.
View Sessions

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