AMIQ EDA at the 2024 Design Automation Conference

AMIQ EDA is a pioneer in integrated development environments (IDEs) for hardware design and verification and a provider of platform-independent software tools for efficient code development and analysis. We’ve been attending DAC for many years and are pleased to do so again in 2024. We exhibit at this show for several reasons. We’re always looking for new users and our booth is a great place for them to check us out. We also meet with many current users, providing updates on what we’re doing and sometimes just saying hello.

As veterans in the EDA industry we know many people from other vendors and organizations, so DAC is a great opportunity to catch up. Finally, the location in San Francisco is just an hour from the heart of Silicon Valley, so we always stay a few extra days to visit users at their facilities. Quite often we will offer a short training course for new users or a presentation on the latest features for those who already know us. Everyone is interested in what’s new and what we’re working on for the future.

So what is new this year? For a start, we have added some cool features for SystemVerilog users to our Design and Verification Tools (DVT) Eclipse IDE and DVT IDE for Visual Studio (VS) Code. We now offer runtime elaboration of Universal Verification Methodology (UVM) code, making it easier to find and fix coding errors within the IDE editor. UVM is a complex verification library with lots of SystemVerilog macros, so the ability to elaborate and check code on the fly is valuable.

We’ve added the ability to precompile or “shallow compile” portions of code to speed up the full build process. This is helpful because verification environments for huge chips are also huge. Not having to compile the full code set all at once saves time and shortens the find-fix-verify loop for coding errors. We’ve also added support for SystemVerilog AMS, reflecting the fact that many of our users are designing mixed-signal chips.

We’ve also significantly improved our ability to handle SystemVerilog files that contain “preprocessor” statements in other languages such as Perl or Python’s Jinja2 library, or even in proprietary languages. Users can edit such files just as if they were pure SystemVerilog. They can take advantage of all their favorite IDE capabilities: navigational hyperlinks, autocomplete, on-the-fly incremental compilation and error detection, quick fixes, refactoring, and more.

We’ve not forgotten our other products. Our Verissimo SystemVerilog Linter now checks around 900 rules, more than 100 of which were added in the past year. Our Specador documentation tool now has a new HTML interface plus support for the PDF and Markdown formats. So, yeah, there’s a lot new to see at DAC. We’re happy to show demos of any features in our booth or to arrange a virtual or physical visit with design and verification teams who may not be at the show.

As we did last year, we’re sponsoring the City Bytes & Beverages Hospitality Zone, where attendees can buy a quick lunch that’s a lot more interesting than the usual convention center hot dogs and frozen pizza. There will be AMIQ EDA signs around to remind everyone that we are long-time supporters of DAC. We invite everyone to stop by our booth!

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