Fast Track Seminars

Atrenta’s SoC realization seminars, “Fast Track Your SoC Design” have started.The first one was in Ottowa last Tuesday, and it was a full house. In a straw poll, most of the attendees acknowledged facing IP handoff and quality issues. The keynote speaker was Dr Yuejian Wu, director of ASIC development at Infinera and an adjuct professor at the University of British Columbia (which seems about as far away as you can get from Ottowa without actually leaving Canada!). He talked about “Fast silicon validation with built-in funcitonal tests.” Other attendees shared their experience with the SpyGlass tools and methodologies. Most of the interest, as judged by the questions, seemed to be on GenSys, Power and Advanced Lint.

The next seminar is coming up next Tuesday, September 27th from noon until 5pm at the Network Meeting Center (5201 Great America Parkway, Santa Clara, by the Hyatt Hotel). The keynote will be Suk Lee, director of design infrastructure marketing at TSMC, another longtime EDA guy who worked for me at one point years ago. He will be speaking about soft IP quality.

The seminar is free and includes lunch (who said there is no such thing as a free lunch) and closes with a cocktail reception.

To register, go here. There is also a seminar in Bangalore on October 13th.