Semiwiki 400x100 1 final
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EDA
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Sagantec 2 Migrate iPad2s @ #48DAC

Sagantec 2 Migrate iPad2s @ #48DAC
by admin on 05-30-2011 at 2:53 pm
Categories: EDA

Sagantec is the leading EDA provider of process migration solutions for custom IC design. Sagantec’s EDA solutions enable IC designers to leverage their investment in existing physical design IP and accomplish dramatic time and effort savings in the implementation of custom, analog, mixed-signal and memory circuits in advanced process technologies.

These solutions have been used commercially by tier-1 semiconductor companies, and have been proven to reduce layout time and effort by factors of 3x to 20x and enable dramatically faster introduction of IC products in new technology nodes.

Apple does not allow iPad2 “giveaways” so Sagantec will be “migrating” iPad2s to a select few conference goers that register for SemiWiki.com. If you are already registered for www.SemiWiki.com just stop by and check-in to qualify for the “migration”.

Sagantec at DAC 2011

Featuring the following presentations and demos:

·Custom, analog and mixed-signal IP migration
·Migration to latest technologies: 40, 32 and 28nm migration
·Automatic PDK update, design rule changes, and DRC correction
·Standard cell library migration and optimization

·Custom, analog mixed-signal IP migration

Migration of custom IP to next process node or different foundry
·Supporting all process technologies
·Maintain and enforce geometric constraints like symmetry, matching, alignments, etc.
·Maintain original design hierarchy and structure
·Support Cadence Virtuoso® IC5 and IC6 database
·Support Pcells and all other Virtuoso data objects
Check out analog IP migration success story

·Migration to latest technologies (including 28nm)

Sagantec migration technology has been used and proven down to 28nm
·Overcoming topology and device changes
·Overcoming new restrictive design rules
·Used an proven on multiple designs
Check out new 28nm migration success story article

·PDK and design rule changes
Adjusting layout to new PDK and design rule changes
·Swap between Pcells and PDKs
·Update new design rule values
·Automatic correction of DRC errors
·Implement recommended DFM rules without changing layout foot-print
·For custom, analog/ mixed-signal blocks and IP
·For large digital blocks and full chips
Check out new PDK adjustment success story article

·Standard Cell Library Migration & Optimization

Migrate, modify and optimize standard cell libraries in the most advanced technologies
·Migrate libraries to next technology node or between foundries
·Supports topology and routing changes (e.g. for 28nm and 22nm)
·Create new library derivatives (HS, LP, etc)
·Analyze and optimize libraries for yield


Process migration Change #tracks

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