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EDA
Posted on by Arabinda Das

Cu-Pillar in Advanced Logic Devices

Cu-Pillar in Advanced Logic Devices
by Arabinda Das on 04-10-2015 at 7:00 pm
Categories: EDA

In 2001, flipchip with solder bump was already a dominant technology and it was replacing wire bonding as the main interconnection choice for a growing number of devices. It was offering fine pitch interconnections for increased I/O counts. In the solder bump process, a bump is formed on the chip and on the package substrate and they are connected by reflow. During the reflow the solder bumps collapse and do not retain their height in two directions. Moreover, the solder bumps occupy a larger space than the pitch of a pad on the chip. These problems frustrated two researchers in IBM and they came out with an alternative solution, called copper pillars (US 6229220 B1).

Their main idea was to have a conducting post that has two metal layers and the lower one has a melting point that is greater than the first layer. According to the teachings of the patent, the difference of melting temperature between these two materials must be greater than 20 C. The lower layer is in contact with the chip substrate and the upper layer with the package substrate. The lower layer could be made of Cu and the upper layer consists of solder. This difference in melting temperature between the two layers is the main innovative concept of the patent. This would help to retain the height of the conducting post during solder reflow. The patent also outlined an integration process to fabricate Cu-pillars, which came to be known as IBM’s Cu-pillar process. This process is widely used in the industry with minor variations. A few years later around 2007, Intel also introduced their concept of Cu-pillars (US7276801B2), which is slightly different from the IBM process-flow. The basic difference is that the conductive pillar is encapsulated with a diffusion barrier as a protective layer.

Very quickly, many researchers started working on this concept and they realized that the bump-pad height, the bump composition and the bump-pitch had an influence on the stress that was transferred to the underlying dielectrics, especially if the dielectrics were made of low-k materials. The stress was coming from the differential thermal expansion coefficient between the Si substrate and the organic printed circuit board. This discovery led to the major improvements in underfill materials and under bump metallization (UBM). The semiconductor industry quickly realized the advantages of this new technology; including: a bump-pitch in the order of 50 µm that could be achieved and thus open up the possibility of higher density of connection. The stand-off height was definitely an edge compared to the conventional C4 solder bumps and facilitated void free underfill. The biggest advantage was the superior electrical and thermal conductance of copper pillars than that of the solder material.

At 65 nm node, two companies introduced copper pillars; the first one was from Intel (Intel Pentium 65 nm D 920 processor) and the second one was ST-Ericsson (ST-Ericsson 65 nm, DB5730 Baseband Processor). Surprisingly, this technology did not take wings as the technology advanced to the next node. At 45/ 40 / 32 nm technology node, several advanced logic processors flooded the market. But only two companies Intel and Texas Instrument employed the Cu-pillar integration scheme. A list of the 45 nm node devices analyzed at TechInsights is given below along with a remark about their packaging process.

[TABLE] border=”1″
|-
| style=”width: 160px” | Company
| style=”width: 160px” | Device
| style=”width: 66px” | Node
| style=”width: 210px” | Packaging
|-
| style=”width: 160px” | Matsushita
| style=”width: 160px” | UniPhier System LSI
| style=”width: 66px” | 45 nm
| style=”width: 210px” | Au ball bond + Wire bonding
|-
| style=”width: 160px” | Intel
| style=”width: 160px” | Penryn Processor QX9650
| style=”width: 66px” | 45 nm
| style=”width: 210px” | Flipchip, Cu-Pillars
|-
| style=”width: 160px” | Apple/Samsung
| style=”width: 160px” | Applications Processor 3[SUP]rd[/SUP] Generation
| style=”width: 66px” | 45 nm
| style=”width: 210px” | Flipchip, Solder bump
|-
| style=”width: 160px” | Texas Instrument
| style=”width: 160px” | X4430SDCCBL OMAP4430 processor
| style=”width: 66px” | 45 nm
| style=”width: 210px” | Flipchip, Cu-Pillars
|-
| style=”width: 160px” | Sony / IBM
| style=”width: 160px” | CXD2992AGB, in the Sony PS3 Slim
| style=”width: 66px” | 45 nm
| style=”width: 210px” | Flipchip, Solder bump
|-
| style=”width: 160px” | AMD
| style=”width: 160px” | Quad-Core-Opteron
| style=”width: 66px” | 45 nm
| style=”width: 210px” | Flipchip, Solder bump
|-
| style=”width: 160px” | Freescale
| style=”width: 160px” | P2020PSE2KZA, Processor
| style=”width: 66px” | 45 nm
| style=”width: 210px” | Au ball bond + Wire bonding
|-
| style=”width: 160px” | Altera Stratix-TSMC
| style=”width: 160px” | IV GX 40 nm, FPGA
| style=”width: 66px” | 40 nm
| style=”width: 210px” | Flipchip, Solder bump
|-
| style=”width: 160px” | ATI-Radeon-AMD-TSMC
| style=”width: 160px” | Graphics processor
| style=”width: 66px” | 40 nm
| style=”width: 210px” | Flipchip, Solder bump
|-
| style=”width: 160px” | AMD-Global foundries
| style=”width: 160px” | AD3850WNGX Processor
| style=”width: 66px” | 32 nm
| style=”width: 210px” | Flipchip, Solder bump
|-
| style=”width: 160px” | Panasonic
| style=”width: 160px” | MN2WS0150 Processor
| style=”width: 66px” | 32 nm
| style=”width: 210px” | Flipchip, Solder bump
|-
| style=”width: 160px” | Intel
| style=”width: 160px” | Clarkdale/Westmere
| style=”width: 66px” | 32 nm
| style=”width: 210px” | Flipchip, Cu-Pillars
|-

The situation is quite different for devices below 30 nm node. There are fewer device makers who can employ this technology beyond 20 nm. Most of the devices are manufactured either by TSMC, by Samsung or by Intel. Intel has continued to use copper pillars in all its technology nodes since the 65 nm node. Samsung is still using solder bump technology even for their 20 nm logic device; while TSMC has adopted Cu-Pillars in their packaging modules and no company is using wire bonding technology in its advanced logic devices.

[TABLE] border=”1″
|-
| style=”width: 160px” | Company
| style=”width: 160px” | Device
| style=”width: 78px” | Node
| style=”width: 174px” | Packaging
|-
| style=”width: 160px” | Xilinx-Kintex-TSMC
| style=”width: 160px” | 7XC 7 XC7K325T; HKMG
| style=”width: 78px” | 28 nm
| style=”width: 174px” | Flipchip, Solder bump
|-
| style=”width: 160px” | ATI-Radeon-TSMC
| style=”width: 160px” | HD7970 Graphics, HKMG planar
| style=”width: 78px” | 28 nm
| style=”width: 174px” | Flipchip, Solder bump
|-
| style=”width: 160px” | Nvidia-TSMC
| style=”width: 160px” | GK107 Garphics, HKMG planar
| style=”width: 78px” | 28 nm
| style=”width: 174px” | Flipchip, Solder bump
|-
| style=”width: 160px” | Mediatek-TSMC
| style=”width: 160px” | MT6592, HKMG planar
| style=”width: 78px” | 28 nm
| style=”width: 174px” | Flipchip, Cu-Pillars
|-
| style=”width: 160px” | Qualcomm-Samsung
| style=”width: 160px” | MDM9215,Poly planar
| style=”width: 78px” | 28 nm
| style=”width: 174px” | Flipchip, Solder bump
|-
| style=”width: 160px” | Intel
| style=”width: 160px” | i5-3550 Ivy Bridge, HKMG, FinFET
| style=”width: 78px” | 22 nm
| style=”width: 174px” | Flipchip, Cu-Pillars
|-
| style=”width: 160px” | Intel
| style=”width: 160px” | Valley View Atom Z3740, HKMG, FinFET
| style=”width: 78px” | 22 nm
| style=”width: 174px” | Flipchip, Cu-Pillars
|-
| style=”width: 160px” | Qualcomm-TSMC
| style=”width: 160px” | MDM9235, HKMG, planar
| style=”width: 78px” | 20 nm
| style=”width: 174px” | Flipchip, Cu-Pillars
|-
| style=”width: 160px” | Samsung
| style=”width: 160px” | Exynos 5430, HKMG planar
| style=”width: 78px” | 20 nm
| style=”width: 174px” | Flipchip, Solder bump
|-
| style=”width: 160px” | Intel
| style=”width: 160px” | Broadwell 5Y70, HKMG, FinFET
| style=”width: 78px” | 14 nm
| style=”width: 174px” | Flipchip, Cu-Pillars
|-

The copper pillars of two highly successful processes in the industry are shown below. Figure 1 is TSMC’s 28 nm node and the Figure 2 is Intel’s 22 nm node. The biggest difference between the two processes is that Intel’s 22 nm bond pad is made of Cu, while the bond pad of TSMC’s 28 nm device is formed in Al.

Figure 1: TSMC 28 nm, Cu-Pillar process on Al bond pad, showing the Cu-pillar pitch

Figure 2: TSMC 28 nm, Cu-Pillar process on Al bond pad, showing the Cu-pillar structure

Figure 3: Intel 22 nm, Cu-Pillar process on Cu bond pad, showing the Cu-pillar pitch

Figure 4: Intel 22 nm, Cu-Pillar process on Cu bond pad, showing the Cu-pillar structure

There are some similarities and differences between the two processes. The cross-sections show that TSMC’s process uses fairly perpendicular copper pillars as compared to Intel’s process. The ratio of Cu to solder is smaller for the Intel process as compared to TSMC process. Intel prefers to employ a narrow neck and a broad shoulder. But both of them employ very relaxed pitches, probably to have a void free underfill. The general process flow is the same and the main steps are given below:

— Pattern the bond pads,
— Deposit the passivation layers on top of the bond pads
— Pattern the openings in passivation to expose the top surface of the bond pad.
— Deposit a polyimide layer on top of the passivation and on the exposed bond pad
— Pattern polyamide to have an opening
— Deposit a barrier layer followed by a seed layer (Cu)
— Apply photo-resist and pattern to form a mold for the pillar
— Electro-deposit the pillar material using the seed layer as a nucleation site
— Cap the Cu-pillar with Ni to prevent oxidation and for adhesion with solder
— Deposit solder on top of the Cu-pillar
— Remove the photo-resist and pattern the barrier layers using the pillar as a mask

The differences are mainly in the geometrical aspects and are summarized in the table below:

Table 1: Cu-pillar dimensions and materials for TSMC and Intel

The Cu-pillar dimensions of these two processes are not at the frontiers of what the Cu-pillar can deliver in terms of fine pitch or standoff heights but these Cu-pillar processes are the fore-runners of the industry. They are designed to dissipate heat effectively and have robust reliability for high performance processors. Adoption of the Cu-pillar is inevitable for advanced logic devices because Cu-pillar technology is one of the key enablers of 3DIC integration. In the future, if Cu-Cu bonding becomes the mainstream then the solder cap on the Cu-pillars will eventually be eliminated. Cu-pillar bump technology is needed for through-silicon-vias (TSV) and for other advanced packaging methods.

That is the reason, why the most recent 20nm DRAM device from Samsung is employing Cu-pillars. Recently, Dr. Kevin Gibb from TechInsights blogged that Samsung’s latest DRAM is TSV enabled (TechInsights – Samsung 20 nm DDR4 TSV Enabled DRAM).Adopting Cu-pillars is the first step for TSV bonding. Companies will realize the superior performance of Cu pillars to solder bumps and will feel the need to adopt the process. Several players for the same process will lead to a greater variety of Cu-pillar designs and the manufacturing cost will be lowered.

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