Predicting Component Temperature Early in Design

In today’s electronics with multiple functions working together, heat generation is on the rise; sometimes it becomes intolerable. In fact components running at different temperatures can cause timing issues, and very high temperatures can lead to operational issues such as latch-up. An electronic system can contain chips, SoCs, PCBs and even fans and heat sinks as cooling systems. In order to see a system working reliably for its lifetime, it’s important to assess the materials, packages, mechanical design of the system, cooling systems and airflow arrangement and so on and estimate the amount of heat it can sustain without damaging the system. And this study and optimization of thermal design of the system has to be done in initial stages of the design, not later. It requires appropriate modeling of component temperatures and then designing the system for it to work under different conditions. So, how do we do this?

The first point is to consider the 3D component model where appropriate packages of the ICs are considered from their thermal conductivity properties. Adding heat sink may not be required if proper selection works well in the simulation. Mentor’sFloTHERM 3D includes material properties in its simulation which can predict case temperature for different package styles. The process to determine the most appropriate component thermal model (CTM) is iterative through continuous refinement.

How to compare the models in the first place to reduce the number of iterations and converge faster in simulation? A 2-resistor CTM is capable of predicting both case and junction temperatures without requiring any more mesh than a simple conducting block, thus having lowest computational burden, but exhibiting worst-case error of the order of ~30% which can vary according to size and type of package. Such models can be used for initial assessment of size of hit sink, number of fins, fin thickness and height needed to reduce the air-side thermal resistance of the heat sink, but not for determining the base thickness needed to adequately spread the heat.

There is JEDEC standard approach for packages with single heat flow path such as LEDs and TO-style packages (used in analog, linear ICs and power semiconductor devices). These packages use RC-laddermodels that include thermal resistors as well as thermal capacitors and can be used for transient simulations. They provide excellent results when the application environment is close to that of the test cold plate environment, for example, when the package is soldered to a MCPCB (Metal-Core PCB). Power LEDs are often mounted on MCPCBs attached to heat sink. Mentor’s T3Ster (transient thermal tester) is used to measure packaged ICs to create such models that can be used directly as a network assembly for 3D thermal simulation in FloTHERM.

DELPHI models are further up in terms of accuracy and can be used for detailed thermal design work of all but the most thermally critical packages such as stacked or 3D ICs where additional information such as temperature distribution on the die surface is needed.

Mentor’s FloTHERM PACK has JEDEC package wizard to generate a representative thermal model of the package based on the package information such as style, body size, and number of leads. The model can be updated when more information becomes available, thus making available 2-resistor, DELPHI, and detailed models for easy refining of the CTM as the design is elaborated.

In detailed model, the temperature variation is predicted throughout the package and dies. In order to predict the temperature distribution on the die, the active power variation over the die’s active surface areas has to be accounted. An SoC can have several power maps according to the circuit functions distributed over it. The leakage power which is a function of local temperature gets exacerbated by the active power. Power analysis tools are used to compute power maps.

The detailed models are validated with experiments and effective thermal resistances and capacitances are calibrated using transient thermal testing techniques. T3Ster is used to measure the response of an actual package, and then the simulation model can be adjusted to fit the experimental response, thus increasing the accuracy level of temperature. The thermal conductivity of the thermal interface material (TIM) can be accurately measured as a function of temperature by using T3Ster DynTIM tool to help choose the most suitable TIM for a particular application.

Read a whitepaperat Mentor website for more details which also provides an example where FloTHERM was used to optimize component placement for a high-speed switch in telecom network.

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