How to Optimize for Power at RTL

Last week I was traveling in Munich attending the MunEDA User Group meetingso I missed a live webinar on the topic of optimizing for power at RTL. I finally got caught up in my email this week and had time to view this 47 minute webinar, presented by Guillaume Boilletof Atrenta. He recommended using a combination of automatic, semi-automatic and manual approaches to reduce power. At the SoC level you can make decisions about power and voltage domain partitions, critical blocks can use manual optimization like course or fine-grained clock gating, and non-critical blocks could use automatic power optimization techniques.

The proposed power optimization flow consists of several steps, beginning with your initial RTL as input to the process, and ending up with a gate-level netlist after logic synthesis, placement and routing.

The first step of Power Estimation is where your RTL or even a netlist is parsed, along with any input stimulus or statistical toggling estimates, then producing power numbers per cycle or averaged over time.

Related – Improve Test Robustness & Coverage Early in Design

There’s an optional Power Calibration step shown in the upper-left of the flow, and this is for designers that want to correlate a gate-level netlist with capacitances for interconnect against RTL numbers. The steps for power calibration are:

SPEF is the interconnect parasitics, SGDC is the SpyGlass Design Constraint File, ACM is the Advanced Capacitance Model, and SIM is your input stimulus. The difference between RTL power estimates and the calibrated should be within 15%.

Another option within the Power Estimation phase is to do a physical-aware step, where you use actual placement information about cells and IP blocks like memory. Timing comes from a path delay calculation, so run times are slower:

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Going back to the power optimization flow the power profiling block is where a designer gets feedback on power estimates for each block in the SoC. Numbers on clock gating efficiency and activity levels provide the designer with analysis to decide which blocks should use clock gating techniques. A power browser displays numbers and a visual GUI to show you which blocks consume the most power.

Clicking on a block you can see more details like the registers, memories, micro-architecture and clocks being used, all opportunities for power reduction techniques.

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There are several sequential power reduction techniques available, one is called stability condition where the enable to a downstream register can be identified and controlled.

Another sequential power reduction technique is called Observability Don’t Care Condition, where the enable to a register can be identified so that it doesn’t toggle node Q and the following logic stays dormant.

Power reduction techniques applied to memories include:

• Input data registers clocked
• Redundant access removal
• Light sleep mode activation

Feedback on how to modify your micro-architecture for lower power can be through FIFO optimization, counter gating and glitchy input identification. Activity trigger detection can find and show you the root causes of power changes from idle to active, spikes or surges.

The RTL Power Verification step in the flow is where you want to double-check that your power goals have been met as specified by UPF 2.0 or 2.1, power lint checks have been run, and that RTL versus power intent is consistent. Power Verification also includes the step where the post-synthesis RTL is checked to be consistent.

Related – A Complete Timing Constraints Solution, Creation to Signoff

The SpyGlass tool suite continues to expand over time, initially starting with lint and now helping RTL designers create power optimized designs. View the entire webinar here including a Q&A session, after a brief registration process.

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