Rise Design Automation at DAC 2026

AI was everywhere at DAC 2026, so I stopped by the booth of Rise Design Automation to chat with Ellie Burns to hear what’s new this year. Ellie shared that Rise DA has added a new AI-powered flow to go from specification to a High Level Synthesis (HLS) model, to a RTL model. The reason for using a HLS model is to gain much more simulation speed, performance, and capacity. Their HLS flow has overcome earlier challenges like QOR and timing.

Their two new tools, IPCreate Platform and IPTransform Platform where written by humans along with some some LLM generated code using tools like Claude code. Using these higher level EDA tools enable an engineer to create about a million gates in a week from a specification, something just not possible with hand-written RTL coding practices.

Design teams have enormous time pressure to get new products out to market in 9 months to a year, then on top of that the specifications are changing quite fast and late in the project, so how do you respond to those late-breaking requirements. RTL coding is too slow for new system bring up, so moving to a higher level language makes sense. Emulation as a methodology does speed up simulations, but it is quite expensive. Higher level languages like MathWorks, C++, SystemC or SystemVerilog are supported in Rise flows.

IPCreate takes a specification in, or even MathWork models, then generates C++, SystemC or SystemVerilog models and after synthesis creates technology-optimized RTL models.

IPtransform goes the other direction from IPcreate by starting from RTL then creating an HLS model and even a specification. IPTransform takes RTL input plus a testbench, then AI is used for reasoning on the elaborated design, it checks claims against the spec, so there are no surprises. The spec is output and can be simulated, and because it raised to a high level model you get the fastest simulation speed. The high level models are 30X faster than RTL models.

By moving the design abstraction level higher there are many benefits: Larger systems for AI enabled, fewer emulators required, many starting points to consider. Trying to use a tool like Claude to go from specification to high level model won’t always work out as intended, because it may generate a model that cannot be synthesized, or worse, has hallucinations in it

Adopting the approach from Rise means that your single source of truth moves up in abstraction and the methodology integrates in with your existing EDA tool flows. With Rise there’s also a way to add timing annotation for RTL-accurate system simulation.

As an example, take a RISC-V system with 5-10 modules along with a written spec, registers defined, and a bus functional model, using a human in the loop, the Rise tools created an IO MMU block in just one hour. That same block would take an RTL expert months to complete. The RTL code generated by Rise is human readable, includes line references, and all of your signal names are preserved.

At DAC they were one of the very few EDA vendors to dare show live demos of complete debug visibility, where you point to a line in the HLS and then see the RTL generated, or you could point to a line of RTL and then see HLS that created it. Rise uses purpose-built AI skills that are grounded in a curated hardware knowledge base that drives their agentic AI for HLS and EDA tools. Users can add their own skills to further extend the tool for their project, department and company.

Power can now be examined in the HLS tools now, so it knows how to pipeline a design to meet power goals, and there aer four levels of power optimization, with block-level clock gating supported. The latest Rise HLS Platform has improved QOR, made debug easier and shortened run times.

RTL synthesis is integrated inside the HLS flow, along with timing-critical path analysis by using open-source tools with feedback given to the HLS scheduler. Rise properly handles designs using advanced nodes, like 5nm and 3nm with accurate timing. HLS reads in the .LIB file for technology specific information, and just the critical paths need to be tech-specific analysis. Even control-dominated designs are now possible with HLS, like a PCI bus.

Summary

I walked away pretty impressed with the progress made at Rise in the past year, as they have added AI technology into their flow, producing deterministic results, enabling design teams to verify their chips up to 100X faster than other methods.

Related Blogs

• 2026 Outlook with Badru Agarwala of Rise Design Automation (RDA)
• Reimagining Architectural Exploration in the Age of AI
• Rise Design Automation Webinar: SystemVerilog at the Core: Scalable Verification and Debug in HLS