Cadence at the 2025 Design Automation Conference #62DAC

Cadence, a DAC 2025 industry sponsor, will exhibit in booth 1609 at the 62nd Design Automation Conference at San Francisco’s Moscone West Convention Center.

Highlights:

Paul Cunningham, SVP and GM of the System Verification Group, Cadence, will speak at Cooley’s DAC Troublemaker Panel. This discussion will be an open Q&A covering interesting and even controversial EDA topics. Monday, June 23, 3:00pm – 4:00pm, DAC Pavilion, Exhibit Hall, Level 2

Cadence will be at the DAC Chiplet Pavilion hosted by EE Times on Level 2, Exhibit Hall Booth 2308:

David Glasco, VP of the Compute Solutions Group, Cadence, will participate in a panel discussion, “Developing the Chiplet Economy.” The commercial chiplet ecosystem is rapidly evolving, driven by the need for greater scalability, performance, and cost efficiency. However, its growth is challenged by the lack of standardized interfaces, industry-wide collaboration, and the complexity of integrating chiplets from multiple vendors. This session will explore the readiness of advanced packaging technologies, the role of design tool vendors, silicon makers, and IP providers, and the collaborative efforts required to establish a thriving chiplet economy. Tuesday, June 24, 2:00pm – 2:55pm.

Brian Karguth, distinguished engineer, Cadence, will present “Cadence SoC Cockpit: Full Spectrum Automation for Chiplet Development.” The semiconductor industry is undergoing a transformation from traditional monolithic system-on-chip (SoC) architectures to modular, chiplet-based designs. This strategic shift is essential to mitigate complexities associated with scaling designs, optimize yields, and address rising fabrication costs driven by increasing transistor costs. To address these challenges, Cadence is offering a full set of chiplet development solutions, including our new Cadence SoC Cockpit, which aims to streamline and optimize the development of next-generation chiplet and system in package (SiP) designs. Learn about Cadence SoC Cockpit and its use for accelerating SoC designs. Tuesday, June 24, 3:50pm – 4:10pm.

Powering the Future: Mastering IEEE 2416 System-Level Power Modeling Standard for Low-Power AI and Beyond: Daniel Cross, senior principal solutions engineer, Cadence, will present a tutorial that will provide attendees with a comprehensive understanding of the IEEE 2416 standard, which is used for system-level power modeling in the design and analysis of integrated circuits and systems. Participants will gain the practical knowledge necessary to implement and utilize the standard effectively. The tutorial will highlight the pressing need for low-power design methodologies, particularly in cutting-edge fields like AI, where computational demands are high. Sunday, June 22, 9:00am – 12:30pm.

Vinod Kariat, CVP and GM of the Custom Products Group, Cadence, will participate in a panel discussion, “The Renaissance of EDA Startups,” on Tuesday, June 24, 2:30pm – 3:15pm.

Cadence will present a series of posters with GlobalFoundries, Intel, IBM, NXP, Samsung, and STMicroelectronics on Tuesday, June 24, 5:00pm – 6:00pm.

A complete list of Cadence activities at DAC can be found at Cadence @ Conference – Design Automation Conference 2025.

Cadence recruiters will be at the DAC Career Development Day on Tuesday, June 24, 10:00am – 3:30pm, inside the entrance of the Exhibit Hall on Level 1. Members of the DAC Community who are considering a job change or a new career opportunity are encouraged to complete an application and upload a résumé/CV, which will be shared in advance with participating employers. Attendees may stop by at any time on Tuesday between 10:00am and 3:30pm to speak with employers.

To arrange a meeting with Cadence at DAC 2025: REQUEST MEETING

DAC registration is open.

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