ISSCC 2026: Samsung shows 16 Gb hybrid bonded Cell-on-Peripheral 4F^2 DRAM

[Fred Chen]

At ISSCC 2026, Samsung demonstrated a 16Gb DRAM with a new 4F^2 vertical channel transistor (VCT) cell architecture. A key achievement was the separation of the circuitry outside the array (core/periphery) from the array on different wafers and the use of hybrid copper bonding to put them together. This allows design rules to be loosened, i.e., features can be spread out more within the same chip area. D1a minimum pitches (~27-28 nm) on a 4F^2 process would give the same cell area (~0.0007-0.0008 um2) as D0a on a 6F^2 process.

https://ieeexplore.ieee.org/document/11409152

 

[Fred Chen]

SK hynix had apparently done the same thing at VLSI 2025, but apparently not at Gb-scale: https://ieeexplore.ieee.org/document/11075066.

Even earlier, in 2023, Micron had unveiled a 32 Gb 4F^2 NVDRAM (Non-Volatile DRAM), which is not only 4F^2 with vertical cell transistors, but also 3D, having two stacked layers on one chip. No wafer bonding was necessary, but the capacitor is in fact ferroelectric, so polarization rather than conventional charge sensing was used. https://ieeexplore.ieee.org/document/10413848