Verifying Leakage Across Power Domains

IC designs need to operate reliably under varying conditions and avoid inefficiencies like leakage across power domains. But how do you verify that connections between IP blocks has been done properly? This is where reliability verification, Electrical Rule Checking (ERC) tools and dynamic simulations all come into play particularly during the verification of leakage between power domains, and other circuit reliability issues.

Let’s look at three types of leakage that need to be verified and voided:

Parasitic leakage – parasitic body diodes, like bulk nodes for PMOS that are not high enough or NMOS not low enough.

Analog gate leakage – MOSFET stacks from power to ground, floating gate inputs, high impedance states.

Digital gate leakage – power domain mismatches, missing level shifters, floating states, high impedance states.

In the following two circuits, (a) has contention when the input is high, while (b) is safe and has no contention for any input state.

Circuit simulation would only catch the contention if the input reached a high state. Static electrical rule checks (ERC) tools do not understand states, so would not find the contention either. Fortunately, there’s a reliability verification solution from Siemens called Insight Analyzer that does use state-based analysis and finds this contention, without resorting to simulation. Circuit designers run Insight Analyzer early and often throughout their design process to quickly find and fix reliability issues, saving valuable engineering time.

Using multiple power domains is a technique to significantly reduce power in complex SoCs, but the interfaces between these domains can have errors like a missing level-shifter or other issues that need to be identified and fixed. Inter-domain leakage between different power domains is challenging to manually verify, so an automated approach is a far more robust approach.

Chips with multiple power domains and low power states need to operate reliably, and the Insight Analyzer tool complements the verification approaches of static checking and dynamic simulation

Circuit simulation at the transistor-level with SPICE is well-known to verify reliability and logic operation, but how do you know if your stimulus has uncovered all the states and modes that are possible to detect a failure or concern? Insight Analyzer catches violations like inter-domain leakage where a backup power supply powers into a main supply that is turned off.

STMicroelectronics

European engineers from STMicroelectronics presented at the 2024 User2User conference on how the Insight Analyzer tool was used in their flow to detect high impedance (HiZ) nets and perform ERC. They wanted to know all instances where HiZ occurred, for both digital and analog circuits to see if they were persistent or transient, and when they caused issues.

Using Insight Analyzer enabled the ST team to verify that high-voltage, high-power, high-density designs were thoroughly verified for reliability issues. Users found that the GUI-based tool had a quick learning curve, allowing them to be operational after just a few hours of use.

Summary

Reliability and leakage issues are critical to verify and fix for multiple power domain designs. Adding reliability verification tools like Insight Analyzer provides immediate benefits to engineering teams. Finding and fixing issues earlier helps to accelerate the schedule for a project.

Read the complete White Paper on Insight Analyzer online.

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