DAC Update on IC Design Tools at Mentor

On Tuesday morning I headed off to the Mentorbooth at DACfor an update on their Custom IC Design and AMS Simulation/Verification tools, Christopher Cone was the presenter. Also in the room were Jay Madiraju, and Mick from Berkeley DA.

Notes

Schematic capture, layout, routing, floor planning, assembly (Pyxis)

SPICE – Eldo Classic, Eldo Premier

Kronos – std cell analysis and characterization

ADMS – Mixed-signal simulation.

ADiT – FastSpice

DRC/LVS/Extraction – Calibre

20 years in the IC business EDA business, thousands of customers.

IC platform – Pyxis (28nm and larger) and PyxisOpen (using OA) are the two choices.

Simulation – setup in the schematic GUI, launch simulators

Waveform viewer – EZwave, ASCII results with AMS Results Browser

Launch jobs like Calibre PERC from the Schematic GUI.

Schematic Driven Layout (SDL)

Interactive routing that is single net, or multiple net, constraint driven, shielding, correct by construction, pushing and jogging, symmetry/mirrored.

Interactive DRC checking with Calibre RealTime, so that you know if the IC layout is clean right away. Also can launch all Calibre tools inside of Pyxis.

Floor planning with Pyxis Assemble. Chip assembly with cost-based routing, called ARoute. The smart router is called Pyxis Custom Router, that is constraint-driven and is qualified for TSMC 28nm.

PDKs – supported by most popular foundries, both MGC PDK (Ample) and iPDK (Tcl and Python) choices available.

XFAB, IBM and TowerJazz support Mentor’s PDK.

TSMC has a 3D reference flow with die-stacking and TSV, Mentor tools work there.

Pyxis allows object rotation, while OA doesn’t, this is needed by MEMS, and silicon photonics. Support for TFT and LCD display designs.

AMS – What’s new is the Berkeley DA acquisition of Analog FastSPICE (AFS) circuit simulator.

Eldo Classic – used for small IP verification and cell characterization.

Eldo Premier – for large transient simulations like PLL, DLL, transceivers. Higher capacity and multi-threading support. AFS does similar simulation. Eldo Premier can speed up from 2x to 15x over Eldo Classic.

Safe Operating Area (SOA) analysis used for IC reliability simulations. Also thermal and aging analysis. Foundries provide models for this type of analysis.

Monte-Carlo analysis supported with save/reuse, auto-stop when confidence level reached, different sampling techniques to reduce the space.

ADiT – traditional FastSPICE circuit simulator, up to 100X faster than SPICE and within 3% accuracy of SPICE. Good for: ADC, DAC, Memory, full-chip power analysis, floating node checks.

A next-generation ADiT for memories and SoCs, capacity of 50M MOS with100M devices, stay tuned.

Questa ADMS – Simulates both HDL and transistor level: VHDL, Verilog, SystemVerilog, SPICE.

Kronos Std Cell characterization and analyzer, works with Eldo and HSPICE simulators.

Design Architect became Pyxis Schematic.

FInFET support – yes, there’s a PDK now and customers are using it for 16nm designs, but with limited capabilities. Stay tuned for the 10.5 release for new features to automate 16nm. Try PyxisOpen for leading edge nodes.

Integrations to Cliosoft and Subversion tools for data management.

What other simulators are supported in Pyxis? Mentor simulators only, but there’s a 3rd party interface to connect with any simulator.

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