Twenty years ago, Blue Pearl showcased its first-generation ASIC and FPGA static verification solution at the 2004 Design Automation Conference. If you are attending DAC 2024, stop by booth 1439 and see how 20 years of product development on the Visual Verification Suite has made chip design much more efficient.
The Visual Verification Suite offers project level verification as you code, for ASIC, FPGA, and IP RTL with advanced RTL structural and formal linting and constraint generation. An optional integrated low-cost glitch, clock and reset domain crossing analysis package, complete with our Advanced Clock Environment providing visualization of clock domains to help designers set up and analyze designs for CDC/RDC caused metastability. The suite’s usability for bug hunting and fixing is proven to help design teams accelerate development while ensuring high reliability designs.
In addition, the suite’s Management Dashboard provides progress reports for audits and design reviews ensuring that all tests have been completed and passed prior to tape out and signoff.
What’s special with our latest release is that we have been partnering with Accellera to develop a standard format to capture CDC/RDC/Glitch intent and have our initial release with the new standard.
The challenge we are addressing is design teams cannot reuse IP-level CDC collateral in their environments if both teams use different CDC verification tools. This scenario is causing a CDC verification problem when the development teams source IP from IP providers that use a different tool for their own CDC verification. To perform holistic top-level verification, additional resources are needed to reconverge the IP with the verification tool used by the other team. Redoing IP-level CDC verification is time consuming and labor intensive.
The Accellera CDC working group’s objective is to develop a standard format to capture CDC/RDC/Glitch intent. This will enable interoperability of CDC collateral generated by different CDC verification tools. The working group is focused on the effort to produce a formal Language Reference Manual. Blue Pearl is actively engaged and adding new features to support this endeavor.
In addition, as an EDA tool provider that tailors to military, aerospace, medical, communications and safety critical design companies our Visual Verification Suite now supports Lattice and EFINIX FPGAs as well as AMD, Intel/Altera, Microchip and NanoXplore SAS FPGAs.
Finally, Adam Taylor a world recognized expert in design and development of embedded s system and FPGA’s , as well as CEO of Adiuvo Engineering and Training will in the BPS booth talking about his use of the Visual Verification Suite and the benefits to his team’s development efforts.
You can contact Blue Pearl here to schedule a meeting at booth #1439 or just stop by. We hope to see you there!
Also Read:
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Silicon Creations at the 2024 Design Automation Conference
Truechip at the 2024 Design Automation Conference
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